• Journal of the Korea Society of Computer and Information
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• v.18 no.1
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• pp.123-136
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• 2013

The Feature model can not be guaranteed the syntactic accuracy of its model and be difficult the validation using automatic tool for its syntax, because this model is expressed by a graphical and informal structure in itself. Therefore, there is a need to formalize and check for the feature model, to precisely define syntax for construct of the model. This paper presents a Z formal specification and a model checking mechanism of the feature model to guarantee the correctness of the model. It first defines the translation rules between feature model and Z, and then converts the syntax of the feature model into the Z schema specification by applying these rules. Finally, the Z schema specification is checked syntax, type, and domain errors using the Z/Eves validation tool to assure the correctness of its specification, With the use of the proposed method, we may express more precisely the construct of the feature model. Moreover the domain analyst are able to usefully verify the errors of the generated feature model.

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.743-751
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• 2007

Model checking has been successfully applied to hardware verification. Software is more subtle than hardware with respect to formal verification due to its infinite state space. Although there are many research activities in this area, bounded model checking is regarded as a promising technique. Bounded model checking uses an upper bound to unroll its model, which is the main advantage of bounded model checking compared to other model checking techniques. In this paper, we applied bounded model checking to verify BIR which is the input model for the model checking tool BOGOR. Some BIR examples are verified with our technique. Experimental results show that bounded model checking is better than explicit model checking provided by BOGOR. This paper presents the formalization of BIR and the encoding algorithm of BIR into CNF.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.385-396
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• 2014

In this paper, we present a formal method for modeling and checking an enhanced version of the carrier sense multiple access with collision avoidance protocol related to the IEEE 802.11 MAC layer, which has been proposed as the standard protocol for wireless local area networks. We deal mainly with the distributed coordination function (DCF) procedure of this protocol throughout a sequence of transformation steps. First, we use the unified modeling language state machines to thoroughly capture the behavior of wireless stations implementing a DCF, and then translate them into the input language of the UPPAAL model checking tool, which is a network of communicating timed automata. Finally, we proceed by checking of some of the safety and liveness properties, such as deadlock-freedom, using this tool.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.995-1004
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• 1998

This paper presents an implementation of model checking tool for LTS process specification, which checks deadlock, livelock and reachability for the state and action. The implemented formal checker using modal mu-calculus is able to verify whether properties expressed in modal logic are true on specifications. We prove experimentally that it is powerful to check, safety and liveness for the state and action on LTS. The tool is implemented by $C^{++}$ language and runs on IBM PC under Windows NT.

• The KIPS Transactions:PartD
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• v.12D no.1 s.97
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• pp.81-90
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• 2005

Given a model and a property, model checking determines whether the model satisfies the property. In case the model does not satisfy the property model checking gives a counterexample which explains where the violation occurs. Since counterexamples are useful for model debugging as well as model understanding, counterexample generation is one of the indispensable components in the model checking tool. This paper presents efficient counterexample generation techniques when a safety property is falsified. These techniques are used to solve Push Push games which consist of 50 games. As a result, all the games are solved with the proposed techniques. However, with the original NuSMV, 42 games are solved but 8 failed. In addition, we obtain $86{\%}$ time improvement and $62{\%}$ space improvement compared to the original NuSMV in solving the game.

• Journal of KIISE:Software and Applications
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• v.35 no.9
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• pp.529-537
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• 2008

Since concurrent software is hard to debug, the verification of such systems inevitably needs automatic tools which support exhaustive searching. Bounded Model Checking (BMC) is one of them. Within a bound k, BMC exhaustively check some errors in execution traces of the given system. In this paper, we introduce the tool that performs BMC for LTS, modeling language for concurrent programs. In this tool, a property is described by a FLTL formula, which is suitable to present the property with actions in a LTS model. To experiment with existential model checkers and out tool, we compare and analysis the performance of the developed tool and others.

• Journal of KIISE
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• v.44 no.10
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• pp.1034-1044
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• 2017

Although traversal strategies are important for the performance of model checking, many studies have ignored the impact of traversal strategies in model checking with a block-encoded abstract reachability graph. Studies have considered traversal strategies only for an abstract reachability graph without block-encoding. Block encoding plays a crucial role in the model checking performance. This paper therefore describes Dual-traversal strategy, a simple and novel technique to control traversal strategies in a block-encoded abstract reachability graph. This method uses two traversal strategies for a model checking, one for effective block-encoding, and the other for traversal in an encoded abstract reachability graph. Dual-traversal strategy is very simple and can be implemented without overhead compared to the existing single-traversal strategy. We implemented the Dual-traversal strategy in an open source model checking tool and compare the performances of different traversal strategies. The results show that the model checking performance varies from the traversal strategies for the encoded abstract reachability graph.

• Journal of Korean Institute of Industrial Engineers
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• v.14 no.2
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• pp.71-80
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• 1988

The primary purpose of this study is to develop an automation tool capable of converting the specification of structured analysis into that of structured design. Structured Analysis and Structured Design Language (SASDL) is a computer-aided description language based on ERA model and particulariged by ISLDM/SEM. The automation tool utilizes the specifications of data flow diagram described in SASDL to produce their corresponding SASDL specification of structure chart. The main idea behind the automatic conversion process is to categorize the bubbles in data flow diagram and to determine the positions of the bubbles in structure chart according to their categories and the relative locations in data flow diagram. To make the problem into manageable size, the whole system is broken down into separate parts called activity units. A great deal of manual jobs, such as checking processes leveling, checking data derivation of processes, deriving structure chart from data flow diagram, checking any inconsistency between data flow diagram and structure chart and so forth, can be automated by using SASDL and conversion tool. The specification of structure chart derived by conversion tool may be used in an initial step of design to be refined by SASDL users.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.931-936
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• 2005

There may be subtle errors in embedded software since its functionality is very complex. Thus formal verification for detecting them is very needed. Model checking is one of formal verification techniques, and SLAM is a well-known software model checking tool for verifying safety properties of embedded C program. In this paper, we develop a software model checker like SLAM for verifying embedded Java program Compared to SLAM, our tool allows to verify liveness properties as well as safety ones. As a result, we verify some desired properties in embedded Java program for controlling REGO robot.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.513-519
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• 2006

As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.