• Title/Summary/Keyword: Min-sum algorithm

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A High Speed LDPC Decoder Structure Based on the HSS (HSS 기반 초고속 LDPC 복호를 위한 구조)

  • Lee, In-Ki;Kim, Min-Hyuk;Oh, Deock-Gil;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.2
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    • pp.140-145
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    • 2013
  • This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

Single-Step Adaptive Offset Min-Sum Algorithm for Decoding LDPC Codes (LDPC 코드의 빠른 복원을 위한 1단으로 구성된 적응적인 오프셋 MS 알고리즘)

  • Lin, Xiaoju;Baasantseren, Gansuren;Lee, Hae-Kee;Kim, Sung-Soo
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.59 no.1
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    • pp.53-57
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    • 2010
  • Low-density parity-check (LDPC) codes with belief-propagation (BP) algorithm achieve a remarkable performance close to the Shannon limit at reasonable decoding complexity. Conventionally, each iteration in decoding process contains two steps, the horizontal step and the vertical step. In this paper, an efficient implementation of the adaptive offset min-sum (AOMS) algorithm for decoding LDPC codes using the single-step method is proposed. Furthermore, the performances of the AOMS algorithm compared with belief-propagation (BP) algorithm are investigated. The algorithms using the single-step method reduce the implementation complexity, speed up the decoding process and have better efficiency in terms of memory requirements.

GPU Algorithm for Outer Boundaries of a Triangle Set (GPU를 이용한 삼각형 집합의 외경계 계산 알고리즘)

  • Kyung, Min-Ho
    • Korean Journal of Computational Design and Engineering
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    • v.17 no.4
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    • pp.262-273
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    • 2012
  • We present a novel GPU algorithm to compute outer cell boundaries of 3D arrangement subdivided by a given set of triangles. An outer cell boundary is defined as a 2-manifold surface consisting of subdivided polygons facing outward. Many geometric problems, such as Minkowski sum, sweep volume, lower/upper envelop, Bool operations, can be reduced to finding outer cell boundaries with specific properties. Computing outer cell boundaries, however, is a very time-consuming job and also is susceptible to numerical errors. To address these problems, we develop an algorithm based on GPU with a robust scheme combining interval arithmetic and multi-level precisions. The proposed algorithm is tested on Minkowski sum of several polygonal models, and shows 5-20 times speedup over an existing algorithm running on CPU.

An Area-efficient Implementation of Layered LDPC Decoder for IEEE 802.11n WLAN (IEEE 802.11n WLAN 표준용 Layered LDPC 복호기의 저면적 구현)

  • Jeong, Sang-Hyeok;Na, Young-Heon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.486-489
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    • 2010
  • This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

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Marriage Problem Algorithm Based on Maximum-Preferred Rank Selection Method (최대 선호도 순위선정 방법에 기반한 결혼문제 알고리즘)

  • Lee, Sang-Un
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.3
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    • pp.111-117
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    • 2014
  • In this paper I propose a simple optimal solution seeking algorithm to a stable marriage problem. The proposed algorithm firstly constructs an $n{\times}n$ matrix of the sum of each gender's preference of the other gender $p_{ij}$. It then selects the minimum sum preference $_{min}p_{ij}$ in the constructed matrix and deletes its corresponding row i and column j. This process is repeated until $i=0{\cap}j=0$, after which the algorithm compares initially or last chosen $_{min}p_{ij}$ its alternatives to finally determine one that yields the maximum marginal increase in preference. When applied to 7 stable marriage problems, the proposed algorithm has improved on initial solutions of existing algorithms.

Code Rate 1/2, 2304-b LDPC Decoder for IEEE 802.16e WiMAX (IEEE 802.16e WiMAX용 부호율 1/2, 2304-비트 LDPC 복호기)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.4A
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    • pp.414-422
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    • 2011
  • This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

A FPGA Design of High Speed LDPC Decoder Based on HSS (HSS 기반의 고속 LDPC 복호기 FPGA 설계)

  • Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.11
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    • pp.1248-1255
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    • 2012
  • LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

A Polynomial-time Algorithm for Choosing the Shortest Transportation Path of Logistic Material (최적 보급수송로 선정을 위한 다항시간 알고리듬)

  • 서성철;정규련
    • Journal of the military operations research society of Korea
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    • v.23 no.2
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    • pp.103-119
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    • 1997
  • This paper considers the shortest path problem combined with Min-Min-Sum objective for solving the problem of the military logistics. This paper develops a polynomial-time algorithm for the optimal solution. To analyze the real combat situation, the ability time and distance time of communication line are considered. The complexities of algorithm between previous study and the algorithm developed in this paper is presented. Finally we provide a simple example of application with randomly generated problem.

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An analysis of BER performance of LDPC decoder for WiMAX (WiMAX용 LDPC 복호기의 비트오율 성능 분석)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.771-774
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    • 2010
  • In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

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Algorithm for the Incremental Augmenting Matching of Min-Distance Max-Quantity in Random Type Quadratic Assignment Problem (랜덤형 2차원 할당문제의 최소 거리-최대 물동량 점진적 증대 매칭 알고리즘)

  • Lee, Sang-Un
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.3
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    • pp.177-183
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    • 2022
  • There is no known polynomial time algorithm for QAP that is a NP-complete problem. This paper suggests O(n2) polynomial time algorithm for random type quadratic assignment problem (QAP). The proposed algorithm suggests incremental augmenting matching strategy that is to set the matching set M={(li,fj)} from li with minimum sum of distance in location matrix L and fj with maximum sum of quantity in facility matrix F, and incremental augmenting of matching set M from M to li with minimum sum of distance and to fj with maximum sum of quantity. Finally, this algorithm performs swap strategy that is to reflect the complex correlations of distances in locations and quantities in facilities. For the experimental data, this algorithm, in spite of O(n2) polynomial time algorithm, can be improve the solution than genetic algorithm a kind of metaheuristic method.