• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.95-95
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• 2014

An OLED(Organic Light-Emitting Diode) device based on the emissive electroluminescent layer a film of organic materials. OLED is used for many electronic devices such as TV, mobile phones, handheld games consoles. ULVAC's mass production systems are indispensable to the manufacturing of OLED device. ULVAC is a manufacturer and worldwide supplier of equipment and vacuum systems for the OLED, LCD, Semiconductor, Electronics, Optical device and related high technology industries. The SMD Series are single-substrate sputtering systems for deposition of films such as metal films and TCO (Transparent Conductive Oxide) films. ULVAC has delivered a large number of these systems not only Organic Evaporating systems but also LTPS CVD systems. The most important technology of thin-film encapsulation (TFE) is preventing moisture($H_2O$) and oxygen permeation into flexible OLED devices. As a polymer substrate does not offer the same barrier performance as glass substrate, the TFE should be developed on both the bottom and top side of the device layers for sufficient lifetimes. This report provides a review of promising thin-film barrier technologies as well as the WVTR(Water Vapor Transmission Rate) properties. Multilayer thin-film deposition technology of organic and inorganic layer is very effective method for increasing barrier performance of OLED device. Gases and water in the organic evaporating system is having a strong influence as impurities to OLED device. CRYO pump is one of the very useful vacuum components to reduce above impurities. There for CRYO pump is faster than conventional TMP exhaust velocity of gases and water. So, we suggest new method to make a good vacuum condition which is CRYO Trap addition on OLED evaporator. Alignment accuracy is one of the key technologies to perform high resolution OLED device. In order to reduce vibration characteristic of CRYO pump, ULVAC has developed low vibration CRYO pumps to achieve high resolution alignment performance between Metal mask and substrate. This report also includes ULVAC's approach for these issues.

• 대한전자공학회논문지SD
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• 제38권7호
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• pp.513-519
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• 2001

Si 과다 텅스텐 실리사이드를 초미세 MOS 소자의 대체 게이트 전극으로 제안하였다. SiO₂위에 텅스텐 실리사이드를 직접 증착하고 급속 열처리를 수행한 결과 낮은 저항을 얻고 불소(F) 확산 또한 무시할 수 있음을 확인하였다. 특히, 800 ℃, 진공 분위기에서 3분간 급속 열처리한 텅스텐 실리사이드의 경우 비저항이 ∼160 μΩ·cm이었고, 불소확산에 의한 산화막의 불균일한 성장도 발견할 수 없었다. 또한, WSix-SiO₂-Si (MOS) 캐패시터의 전기적 특성 분석 결과도 우수하였다.

• 센서학회지
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• 제24권2호
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• Journal of the Korean Physical Society
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• 제73권10호
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• pp.1444-1451
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• 2018

The surface-to-volume ratio of one-dimensional (1D) semiconductor metal-oxide sensors is an important factor for achieving good gas sensing properties because it offers a wide response area. To exploit this effect, in this study, we determined the optimal calcination temperature to maximize the specific surface area and thereby the sensitivity of the sensor. The $In_2O_3$ nanorods were synthesized by using vapor-liquid-solid growth of $In_2O_3$ powders and were decorated with the Pt nanoparticles by using a sol-gel method. Subsequently, the Pt nanoparticle-decorated $In_2O_3$ nanorods were calcined at different temperatures to determine the optimal calcination temperature. The $NO_2$ gas sensing properties of five different samples (pristine uncalcined $In_2O_3$ nanorods, Pt-decorated uncalcined $In_2O_3$ nanorods, and Pt-decorated $In_2O_3$ nanorods calcined at 400, 600, and $800^{\circ}C$) were determined and compared. The Pt-decorated $In_2O_3$ nanorods calcined at $600^{\circ}C$ showed the highest surface-to-volume ratio and the strongest response to $NO_2$ gas. Moreover, these nanorods showed the shortest response/recovery times toward $NO_2$. These enhanced sensing properties are attributed to a combination of increased surface-to-volume ratio (achieved through the optimal calcination) and increased electrical/chemical sensitization (provided by the noble-metal decoration).

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• 한국진공학회지
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• 제7권3호
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• pp.195-200
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• 1998

본 연구에서는 강유전체 박막의 게이트 산화물로 사용한 $Pt/SrBi_2Ta_2O_9(SBT)/CeO_2/Si(MFS)$와 Pt/SBT/Si(MFS) 구조의 결정 구조 및 전기적 성질 의 차이를 연구하였다. XRD 및 SEM 측정 결과 SBT/$CeO_2$/Si박막은 약5nm정도의 $SiO_2$층 이 형성되었고 비교적 평탄한 계면의 미세구조를 가지는 반면, SBT/Si는 각각 약6nm와 7nm정도의 $SiO_2$층과 비정질 중간상층이 형성되었음을 알 수 있다. 즉 CeO2 박막을 완충층 으로 사용함으로써 SBT박막과 Si기판의 상호 반응을 적절히 억제할 수 있음을 확인하였다. Pt/SBT/$CeO_2/Pt/SiO_2$/와 Pt/SBT/Pt/$SiO_2$/Si구조에서 Polarization-Electric field(P-E) 특 성을 비교해 본 결과 CeO2박막의 첨가에 따라 잔류분극값은 감소하였고 항전계값은 증가하 였다. MFIS구조에서 memory window값은 항전계값과 직접적 관련이 있으므로 이러한 항 전계값의 증가는 MFIS구조에서의 memory window값이 증가할 수 있음을 나타낸다. Pt-SBT(140nm)/$CeO_2$(25nm)/Si구조에서 Capacitance-Voltage(C-V) 측정 결과로부터 동작 전압 4-6V에서 memory wondows가 1-2V정도로 나타났다. SBT박막의 두께가 증가할수록 memory window값은 증가하였는데 memory wondows가 1-2V정도로 나타났다. SBT박막의 두께가 증가할수록 memory window값은 증가하였는데 이는 SBT박막에 걸리는 전압강하가 증가하기 때문인 것으로 생각되어진다. Pt/SBT/$CeO_2$/Si의 누설전류는 10-8A/cm2정도였고 Pt/SBT/Si 구조에서는 약10-6A/cm2정도로 약간 높은 값을 나타내었다.

• 한국결정성장학회지
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• 제31권4호
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• pp.149-153
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• 2021

ε-Ga₂O₃ 박막은 금속 유기 화학 기상 증착법(MOCVD)에 의해 4H-SiC 기판에 성장되었으며, 결정성은 성장 조건에 따라 평가되었다. ε-Ga₂O₃의 최적 조건은 665℃의 성장 온도와 200 sccm의 산소 유량에서 성장한 것으로 나타났다. hexagonal 핵이 합쳐지면서 2차원으로 성장되었고, hexagonal 핵의 배열 방향은 기판의 결정 방향과 밀접한 관련이 있었다. 그러나 ε-Ga₂O₃의 결정 구조는 hexagonal이 아닌 orthorhombic 구조를 가짐을 확인하였다. 결정상 전이는 열처리에 의해 수행되었다. 그리고 상 전이된 β-Ga₂O₃ 박막과 비교하기 위해 4H-SiC에서 β-Ga₂O₃ 박막을 바로 성장하였다. 상 전이된 β-Ga₂O₃ 박막은 바로 성장한 것보다 더 나은 결정성을 보여주었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• 한국진공학회지
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• 제22권5호
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• pp.245-249
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• 2013

MOSFET 구조의 차세대 Oxide 박막으로 주목받고 있는 $HfO_X$박막을 rf magnetron sputter를 이용하여 Si(100) 기판 위에 증착하였다. 증착시 산소의 유량을 5, 10, 15 sccm으로 변화를 주며 증착하였고 이후 furnace에서 400부터 $800^{\circ}C$까지 질소분위기로 열처리 하였다. 실험결과 $HfO_X$ 박막의 전기적 특성은 산소유량 증가에 따라 누설전류 특성이 향상되었으나, 열처리 온도가 증가함에 따라서는 감소하였다. 특히, 이 논문에서는 Nano-indenter와 AFM으로 $HfO_X$ 박막의 nanomechanics 특성을 측정하였다. 측정 결과에 의하면 열처리 온도가 증가함에 따라 최대 압입력을 기준으로 최대 압입 깊이가 24.9 nm에서 38.8 nm로 증가하였으며 특히 $800^{\circ}C$ 열처리된 박막에서 압입 깊이가 급격하게 증가하였다. 이러한 압입 깊이의 급격한 증가는 박막내 응력 완화에 의한 스트레스 변화로 예상되며, 그 원인으로 증착시 박막내 포함된 산소가 열처리 조건에 의해 빠져나감에 의한 것으로 판단된다.

• 센서학회지
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• 제28권1호
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• pp.41-46
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• 2019

In order to develop novel thermal imaging materials for microbolometer applications, $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ ($0.18{\leq}x{\leq}0.26$) thin films were fabricated using metal-organic decomposition. Effects of Cu content on the electrical properties of the annealed films were investigated. Spinel thin films with a thickness of approximately 100 nm were obtained from the $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ films annealed at $380^{\circ}C$ for five hours. The resistivity (${\rho}$) of the annealed films was analyzed with respect to the small polaron hopping model. Based on the $Mn^{3+}/Mn^{4+}$ ratio values obtained through x-ray photoelectron spectroscopy analysis, the hopping mechanism between $Mn^{3+}$ and $Mn^{4+}$ cations discussed in the proposed study. The effects of $Cu^+$ and $Cu^{2+}$ cations on the hopping mechanism is also discussed. Obtained results indicate that $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ thin films with low temperature annealing and superior electrical properties (${\rho}{\leq}54.83{\Omega}{\cdot}cm$, temperature coefficient of resistance > -2.62%/K) can be effectively employed in applications involving complementary metal-oxide semiconductor (CMOS) integrated microbolometer devices.