• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.7
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• pp.9-16
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• 2011

In this paper, various kinds of high throughput turbo decoding schemes are introduced, and a new turbo decoding scheme using the advantages of each scheme is proposed. The proposed scheme uses the decoding structure of double flow scheme, sliding window scheme and shuffled turbo decoding scheme. Simulation results show that the proposed scheme offers a BER performance equivalent to those of existing turbo decoding schemes with less clock cycles. We also show that the required memory can be reduced by choosing proper size of sliding window. Consequently, we can design a high throughput turbo decoder requiring low power and low area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.117-124
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• 1998

As window sized increases, the throughput input-buffered packet switch with a window scheme improves on random traffic condition. However, the improvement diminishes quickly under bursty traffic. In this paper, we propose Burst Head Addressable FIFO mechanism and memory structure having search capability in unit of burst header to compensate the sensitiveness of the windowed scheme to bursty traffic. The performance of a input-buffered switch using the proposed Burst Header Addressable FIFO input buffer was analyzed using computer simulations. The maximum throughput of the conventional FIFO scheme approaches an asymptotic value 0.5 as mean burst length increases. The maximum throughput of the proposed scheme is greater than that of the conventional scheme for any mean burst length and window size.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.775-783
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• 1990

In this paper we implemented the fast thinning unit by modifying the pipeline architecture which was proposed by Stanley R. Sternberg. The unit is useful in preprocessing such as image representation and pattern recognition etc. This unit is composed of interface part, local memory part, address generation part, thinning processing part and control part. In thinning processing part, we shortened the thinning part which performed by means of look up table using window mapping table. Thus we improved the weakness of SAP, in which the number of delay pipeline and window pipeline are equal to image column size. Two independent memorys using tri-state buffer enable the two direction flow of address generated by address generation part. This unit avoids the complexity of architecture and has flexibility of image size by means of simple modification of logic bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.273-279
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• 2001

본 논문에서는 LCD MW를 이용한 각다중화 시스템에서 인접한 수직방향 MW사이에서 발생하는 영상누화현상에 대해 분석하였다. LCD MW를 이용한 각다중화 방법으로 LCD 상에서 수평, 수직방향으로 움직이는 각 창들을 통과한 기준빔이 서로 다른 파벡트로 입사되기 때문에 이러한 창들의 전자적인 제어만으로 효과적인 각다중화된 홀로그램을 얻을 수 있다. 그러나, 수직방향으로 인접한 MW 사이에서 영상누화가 발생하기 때문에 공간적으로 고밀도의 정보저장 및 복원이 제한되고 있다. 따라서, 본 논문에서는 고밀도의 정보저장을 위해 여러 가지 요소들에 의한 영상누화를 이론적으로 분석하고 이에 대한 광학 실험 결과를 제시하였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.405-406
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• 2008

This paper presents a high performance 2D PE architecture for H.264 Motion Estimation(ME). While existing 2D PE architectures reuse the overlapped data of adjacent search windows scanned in 1 or 3-way, the new architecture scan adjacent windows and multiple paths instead of single raster and zigzag scanning of adjacent windows in 4 way(up,down,left,right). By reducing the redundant access factor by 1.4, the new 4-way search window improve the memory bandwidth by 70-58% compared with 1/3-way search window. With Altera Stratix-III implementation, the high performance 2D PE architecture deals with SD ($720{\times}480$) video of 2 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps at 97.1MHz.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.109-110
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• 2006

The performance of a digital baseband signal processing and data transmission rate depends on the modulation technique. In this paper, We implemented DSP communication system for Underwater acoustic communication using by adaptive BPSK modem technique. In order to implement adaptive modem, we suggested SNR detection block. SNR detection block has the reference SNR value that selects between window filter path and matched filter path. In this paper, suggested system is based on software interface and all Hardware(PLL, modem filter, equalizer etc) is implemented by software, exclusive of DSP, A/D, D/A converter, SDRAM and Flash memory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.156-157
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• 2012

단일 셀에서 비휘발성 및 고속의 휘발성 메모리를 모두 구동할 수 있는 다기능 메모리는 모바일 기기 및 embedded 장치의 폭발적인 성장에 있어 그 중요성이 커지고 있다. 따라서 최근 이러한 fusion기술을 응용한 unified RAM (URAM)과 같은 다기능 메모리의 연구가 주목 받고 있다. 이러한 다목적 메모리는 주로 silicon on insulator (SOI)기반의 1T-DRAM과 SONOS기술 기반의 비휘발성 메모리의 조합으로 이루어진다. 하지만 이런 다기능 메모리는 주로 단결정기반의 SOI wafer 위에서 구현되기 때문에 값이 비싸고 사용범위도 제한되어 있다. 따라서 이러한 다기능메모리를 다결정 실리콘을 이용하여 제작한다면 기판에 자유롭게 메모리 적용이 가능하고 추후 3차원 적층형 소자의 구현도 가능하기 때문에 다결정실리콘 기반의 메모리 구현은 필수적이라고 할 수 있겠다. 본 연구에서는 다결정실리콘을 이용한 channel recessed구조의 다기능메모리를 제작하였으며 각 1T-DRAM 및 NVM동작에 따른 memory 특성을 살펴보았다. 실험에 사용된 기판은 상부 비정질실리콘 100 nm, 매몰산화층 200 nm의 SOI구조의 기판을 이용하였으며 고상결정화 방법을 이용하여 $600^{\circ}C$ 24시간 열처리를 통해 결정화 시켰다. N+ poly Si을 이용하여 source/drain을 제작하였으며 RIE시스템을 이용하여 recessed channel을 형성하였다. 상부 ONO게이트 절연막은 rf sputter를 이용하여 각각 5/10/5 nm 증착하였다. $950^{\circ}C$ N2/O2 분위기에서 30초간 급속열처리를 진행하여 source/drain을 활성화 하였다. 계면상태 개선을 위해 $450^{\circ}C$ 2% H2/N2 분위기에서 30분간 열처리를 진행하였다. 제작된 Poly Si MFM에서 2.3V, 350mV/dec의 문턱전압과 subthreshold swing을 확인할 수 있었다. Nonvolatile memory mode는 FN tunneling, high-speed 1T-DRAM mode에서는 impact ionization을 이용하여 쓰기/소거 작업을 실시하였다. NVM 모드의 경우 약 2V의 memory window를 확보할 수 있었으며 $85^{\circ}C$에서의 retention 측정시에도 10년 후 약 0.9V의 memory window를 확보할 수 있었다. 1T-DRAM 모드의 경우에는 약 $30{\mu}s$의 retention과 $5{\mu}A$의 sensing margin을 확보할 수 있었다. 차후 engineered tunnel barrier기술이나 엑시머레이저를 이용한 결정화 방법을 적용한다면 device의 특성향상을 기대할 수 있을 것이다. 본 논문에서는 다결정실리콘을 이용한 다기능메모리를 제작 및 메모리 특성을 평가하였다. 제작된 소자의 단일 셀 내에서 NVM동작과 1T-DRAM동작이 모두 가능한 것을 확인할 수 있었다. 다결정실리콘의 특성상 단결정 SOI기반의 다기능 메모리에 비해 낮은 특성을 보여주었으나 이는 결정화방법, high-k절연막 적용 및 engineered tunnel barrier를 적용함으로써 해결 가능하다고 생각된다. 또한 sputter를 이용하여 저온증착된 O/N/O layer에서의 P/E특성을 확인함으로써 glass위에서의 MFM구현의 가능성도 확인할 수 있었으며, 차후 system on panel (SOP)적용도 가능할 것이라고 생각된다.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.270-275
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• 2000

The Pt/YMnO$_3$/Y$_2$O$_3$/Si structure for metal/ferroelectric/insulator/semiconductor(MFIS)-FET was fabricated and effect of $Y_2$O$_3$layer on the properties of MFIS structure was investigated. The $Y_2$O$_3$ thin films on p-type Si(111) substrate deposited by Pulsed Laser Deposition were crystallized along (111) orientation irrespective of the deposition temperatures. Ferroelectric YMnO$_3$ thin films deposited directly on p-type Si (111) by MOCVD resulted in Mn deficient layer between Si and YMnO$_3$. However, YMnO$_3$ thin films having good quality and stoichiometric composition can be obtained by adopting $Y_2$O$_3$ buffer layer. The memory window of the $Y_2$O$_3$thin films with YMnO$_3$ film is greater than that of the YMnO$_3$ thin films without $Y_2$O$_3$ film after the annealing at 85$0^{\circ}C$ in vacuum ambient(100mtorr). The memory window is 1.3V at an applied voltage of 5V.