• 한국컴퓨터정보학회논문지
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• 제22권9호
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• 전자통신동향분석
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• 제35권3호
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• 대한임베디드공학회논문지
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• 제12권3호
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• pp.177-184
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• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

• 대한전자공학회논문지
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• 제27권6호
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.61-67
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• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.

• Macromolecular Research
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• 제16권7호
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• pp.644-650
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• 2008

This study examined the effect of nanoclays on the shape memory behavior of polyurethane (PU) in fibrous form. A cation was introduced into the PU molecules to disperse the organo-nanoclay (MMT) into poly($\varepsilon$-caprolactone) (PCL)-based PU (PCL-PU). The MMT/PCL-PU nanocomposites were then spun into fibers through melt-processing. The shape memory performance of the spun fibers was examined using a variety of thermo-mechanical tests including a new method to determine the transition temperature of shape memory polymers. The MMTs showed an improved the fixity strain rate of the MMT /PCL- PU fibers but a slight decrease in their recovery strain rate. This was explained by the limited movement of PU molecules due to the presence of nanoclays. The shape memory performance of the MMT/PCL-PU fibers was not enhanced significantly by the nanoclays. However, their recovery power was improved significantly up to a strain of approximately 50%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.167-168
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• 2007

Design Rule이 작아짐에 따라 Transistor performance 향상을 위한 여러 방안중 SEG 공정이 적용되고 있으며 이에 따른 Transistor 특성 연구 결과이다. SEG공정 적용시 SEG Profile에 따라 Transistor의 Short Channel Effect 열화가 발생하였고 그 원인은 Sidewall Facet발생으로 추정되며 이를 개선시 Tr 특성이 개선됨을 확인하였다.

• International Journal of Internet, Broadcasting and Communication
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• 제15권1호
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• pp.79-84
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• 2023

Due to the rapid performance improvement of smartphones, multitasking on mobile platforms has become an essential feature. Unlike traditional desktop or server environments, mobile applications are mostly interactive jobs where response time is important, and some applications are classified as real-time jobs with deadlines. When interactive and real-time jobs run concurrently, memory allocation between multitasking applications is a challenging issue as they have different time requirements. In this paper, we study how to allocate memory space when real-time and interactive jobs are simultaneously executed in a smartphone to meet the multitasking requirements between heterogeneous jobs. Specifically, we analyze the memory size required to satisfy the constraints of real-time jobs and present a new model for allocating memory space between heterogeneous multitasking jobs. Trace-driven simulations show that the proposed model provides reasonable performance for interactive jobs while guaranteeing the requirement of real-time jobs.

• 정보과학회 논문지
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• 제44권2호
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• pp.124-131
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• 2017

고성능 컴퓨팅 환경을 위해서 최근 등장한 차세대 매니코어 프로세서는 전통적인 구조의 메모리와 함께 고대역 온-패키지 메모리를 장착하고 있다. Intel Xeon Phi Knights Landing(KNL) 프로세서의 온-패키지 메모리인 Multi-Channel DRAM(MCDRAM)은 기존의 DDR4 메모리보다 이론적으로 네 배 높은 대역폭을 제공한다. 본 논문에서는 MCDRAM을 이용하여 MPI 노드 내 통신 성능을 향상시키기 위한 방안을 제안한다. 실험 결과, 제안된 기법을 사용할 경우 DDR4를 사용하는 경우와 비교해서 MPI 노드 내 통신 성능을 최대 272% 향상시킬 수 있음을 보인다. 또한 MCDRAM 활용 방법에 따른 성능 영향뿐만 아니라 프로세스의 코어 친화도에 따른 성능 영향을 보인다.

• 한국전자통신학회논문지
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• 제10권2호
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• pp.275-282
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• 2015

NAND 플래쉬메모리는 전원이 꺼져도 데이터를 유지할 수 있고 저비용, 고용량의 특징을 가지기 때문에 휴대용 기기에서 많이 활용되고 있다. 플래쉬메모리에서 대용량의 데이터를 효과적으로 처리하기 위하여 색인을 필수적으로 사용해야 한다. 그러나 플래쉬메모리는 쓰기 연산의 비용이 크고 덮어쓰기 연산을 지원하지 않기 때문에 기존의 디스크기반 색인을 사용하면 성능이 저하되는 문제가 발생할 수 있다. 본 논문에서는 플래쉬메모리에서 고정그리드화일 색인을 구현하고 다양한 조건에서 성능 평가를 수행한다. 이를 위하여 질의연산과 변경 연산의 비율에 따른 평균 수행 시간을 측정한다. 그리고 디스크에서의 수행 시간과 비교한다.