• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1170-1182
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• 2004

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Experimental results show that the proposed architecture achieves a high performance for real time motion estimation.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.205-205
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• 2021

Surface soil moisture, which governs the partitioning of precipitation into infiltration and runoff, plays an important role in the hydrological cycle. The assimilation of satellite soil moisture retrievals into a land surface model or hydrological model has been shown to improve the predictive skill of hydrological variables. This study aims to improve streamflow prediction with Weather Research and Forecasting model-Hydrological modeling system (WRF-Hydro) by assimilating Soil Moisture Active and Passive (SMAP) data at 3 km and analyze its impacts on hydrological components. We applied Cumulative Distribution Function (CDF) technique to remove the bias of SMAP data and assimilate SMAP data (April to July 2015-2019) into WRF-Hydro by using an Ensemble Kalman Filter (EnKF) with a total 12 ensembles. Daily inflow and soil moisture estimates of major dams (Soyanggang, Chungju, Sumjin dam) of South Korea were evaluated. We investigated how hydrologic variables such as runoff, evaporation and soil moisture were better simulated with the data assimilation than without the data assimilation. The result shows that the correlation coefficient of topsoil moisture can be improved, however a change of dam inflow was not outstanding. It may attribute to the fact that soil moisture memory and the respective memory of runoff play on different time scales. These findings demonstrate that the assimilation of satellite soil moisture retrievals can improve the predictive skill of hydrological variables for a better understanding of the water cycle.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• The Journal of the Korea Contents Association
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• v.12 no.3
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• pp.77-83
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• 2012

In this paper, a low-complexity embedded compression (EC) Codec algorithm for the wavelet video coder is applied to reduce excessive external memory requirements. The EC algorithm is used to achieve a fixed compression ratio of 50 % under the near-lossless-compression constraint. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform stages compared with direct implementation of the wavelet video encoder of this paper. Furthermore, the EC scheme based on a forward adaptive quantization and fixed length coding can save bandwidth and size of buffer between DWT and SPIHT to 50 %. Simulation results show that our EC algorithm present only PSNR degradation of 0.179 and 0.162 dB in average when the target bit-rate of the video coder are 1 and 0.5 bpp, respectively.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• The Journal of the Korea Contents Association
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• v.22 no.8
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• pp.81-93
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• 2022

Recently, research on processing a large-capacity graph using GPUs has been conducting. In order to process a large-capacity graph in a GPU with limited memory, the graph must be divided into subgraphs and then processed by scheduling subgraphs. In this paper, we propose an efficient graph algorithm processing scheme in GPU environments with limited memory and performance evaluation. The proposed scheme consists of a graph differential subgraph scheduling method and a graph segmentation method. The bulk graph segmentation method determines how a large-capacity graph can be segmented into subgraphs so that it can be processed efficiently by the GPU. The differential subgraph scheduling method schedule subgraphs processed by GPUs to reduce redundant transmission of the repeatedly used data between HOST-GPUs. It shows the superiority of the proposed scheme by performing various performance evaluations.

• The Journal of the Korea Contents Association
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• v.7 no.1
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• pp.32-39
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• 2007

An important application domain for online services is an interactive, multi-player game. In recent, many increase of users that use on-line services through networks have caused a heavy load to the server. In this paper, we propose a MMORPG(Massively Multi-player Online Role Playing Game) distributed game server using flayer-Cell. Our method provides efficient solution of a MMORPG distributed game server for large numbers of users. It is shown through the experiments that our method outperforms existing methods in terms of memory utilization rate and processing speed.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.850-853
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• 2005

This paper presents issues of display hardware architecture, relating to memory, display driver IC architecture, and chip-to-chip interface. To achieve a low power and low cost mobile phone, not only the display architecture must be carefully selected, but also the driver-ICs optimized to accommodate the different modes of operation found in typical handheld devices. The technique of forming a photo sensor in each pixel using TFT and display module architecture are developed to add multi functions in display such as fingerprint recognition, image scanning, and integrated touch screen. Detailed architectures of IC partitioning, high-speed serial interface, D/A converter, and multi functions such as fingerprint recognition and image scanning using photo sensors are important to a power optimized system.