• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.181.1-181.1
• /
• 2015

용액 공정을 이용한 Resistive random access memory (ReRAM)은 간단한 공정 과정, 대면적화, 저렴한 가격 등의 장점으로 인해 큰 관심을 받고 있으며, HfOx, TiOx, AlOx 등의 산화물이 ReRAM 절연 막으로 주로 연구되고 있다. 더 나아가 최근에는 organic 물질을 메모리 소자로 사용한 연구가 보고되고 있다. 이는 경제적이며, wearable 또는 flexible system에 적용이 용이하다. 그럼에도 불구하고, organic 물질을 갖는 메모리 소자는 기존의 산화물 소자에 비해 열에 취약하며 전기적인 특성과 신뢰성이 우수하지 못하다는 단점을 가지고 있다. 이를 위한 방안으로 본 연구에서는 AlOx - polymethylmethacrylate (PMMA) blended thin film ReRAM을 제안하였다. 이는 organic물질의 전기적 특성을 개선시킬 뿐 아니라, inorganic 물질을 wearable 소자에 적용했을 때 발생하는 crack과 같은 기계적 물리적 결함을 해결할 수 있는 새로운 방법이다. 먼저, P-type Si 위에 습식산화를 통하여 SiO2 300 nm 성장시킨 기판을 사용하여 electron beam evaporation으로 10 nm의 Ti, 100 nm의 Pt 층을 차례로 증착하였다. 그리고 PMMA 용액과 AlOx 용액을 초음파를 이용하여 혼합한 뒤, 이 용액을 Pt 하부 전극 상에서 spin coating방법으로 1000 rpm 10초, 5000 rpm 30초의 조건으로 증착하였다. Solvent 및 불순물 제거를 위하여 150, 180, $210^{\circ}C$의 온도로 30 분 동안 열처리를 진행하였고, shadow mask를 이용하여 상부 전극인 Ti를 sputtering 방식으로 100 nm 증착하였다. 150, 180, $210^{\circ}C$로 각각 열처리한 AlOx - PMMA blended ReRAM의 전기적 특성은 HP 4156B semiconductor parameter analyzer를 이용하여 측정하였다. 측정 결과 제작된 소자 전부에서 2 V이하의 낮은 동작전압, 안정된 DC endurance (>150cycles), 102 이상의 높은 on/off ratio를 확인하였고, 그 중 $180^{\circ}C$에서 열처리한 ReRAM은 더 높은 on/off ratio를 갖는 것을 확인하였다. 결론적으로 baking 온도를 최적화하였으며 AlOx - PMMA blended film ReRAM의 우수한 메모리 특성을 확인하였다. AlOx-PMMA blended film ReRAM은 organic과 inorganic의 장점을 갖는 wearable 및 system용 비휘발성 메모리소자에 적용이 가능한 경제적인 기술로 판단된다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.11a
• /
• pp.30.1-30.1
• /
• 2009

정보화가 급속히 진전됨에 따라 보다 많은 양의 정보를 전송, 처리, 저장하게 되면서 이를 위해 대용량, 고속, 비휘발성의 특징을 갖는 차세대 메모리의 개발이 절실히 요구되고있다. 이 중 저항 변화 메모리(ReRAM)는 일반적으로 TiO2, Al2O3, NiO2, HfO2, ZrO2 등의 전이금속산화물을 이용한 MIM 구조로서 적당한 전기 신호를 가하면 저항이 높아서 전도되지 않는 상태(Offstate)에서 저항이 낮아져 전도가 가능한 상태(On state)로 바뀌는 메모리 특성을가진다. ReRAM은 비휘발성 메모리이며 종래의 비휘발성 기억소자인 Flash memory 보다 access time 이105 배 이상 빠르고, 5V 이하의 낮은 전압에서도 동작이 가능하다. 또한 구조가 간단하여 공정 단순화가 가능하고 소자의 집적화도 쉽다는 점 등 많은 장점들이 있어서 Flash memory를 대체할 수 있는 유력한 후보로 여겨지고 있다. 본연구에서는 DC-magnetron Sputtering 방법으로 전이금속 박막을 증착하고, Dry furnace로 산화시켜 전이금속산화물 박막을 제작한 후 저항변화 특성을 연구하였다. 두 개의 전이금속산화물 박막을 dual-layer로 형성시켜 저항변화특성을 관찰하였으며 또한, 전이금속산화물 박막의 조성을 달리 하여 저항변화를 관찰 하였다. 전이금속산화물 박막의 전기적 특성을 알아보기 위해 Si(100) wafer 위에 Pt를 이용 MIM 형태로 capacitor 시편을 제작 하여, probe station으로 I-V 측정을 하였고 조성 및 표면 분석을 위해서는 AES와 AFM을, 미세구조를 분석을 위해서는 TEM과 SEM 을 사용하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.52-52
• /
• 2009

To date, chalcogenide alloy such as $Ge_2Sb_2Te_5$(GST) have not only been rigorously studied for use in Phase Change Random Access Memory(PRAM) applications, but also temperature gap to make different states is not enough to apply to device between amorphous and crystalline state. In this study, we have investigated a new system of phase change media based on the In-Sb-Te(IST) ternary alloys for PRAM. IST chalcogenide thin films were prepared in trench structure (aspect ratio 5:1 of length=500nm, width=100nm) using Tri methyl Indium $(In(CH_3)_4$), $Sb(iPr)_3$ $(Sb(C_3H_7)_3)$ and $Te(iPr)_2(Te(C_3H_7)_2)$ precursors. MOCVD process is very powerful system to deposit in ultra integrated device like 100nm scaled trench structure. And IST materials for PRAM can be grown at low deposition temperature below $200^{\circ}C$ in comparison with GST materials. Although Melting temperature of 1ST materials was $\sim 630^{\circ}C$ like GST, Crystalline temperature of them was ~$290^{\circ}C$; one of GST were $130^{\circ}C$. In-Sb-Te materials will be good candidate materials for PRAM applications. And MOCVD system is powerful for applying ultra scale integration cell.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.10
• /
• pp.467-473
• /
• 2007

Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency. The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power consumption caused by data transfers over the conventional method in MC module.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.12
• /
• pp.4997-5006
• /
• 2010

A flash-memory-based SSDs(Solid State Disks) are one of the best media to support portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major database storage components for desktop and server computers. However, we need to improve traditional storage management schemes based on HDD(Hard Disk Drive) and RAID(Redundant array of independent disks) due to the relatively slow or freezing characteristics of write operations of SSDs, as compared to fast read operations. In order to achieve this goal, we propose a new storage management scheme called Hetero-Mirroring based on traditional HDD mirroring scheme. Hetero-Mirroring-based scheme improves RAID-1 operation performance by balancing write-workloads and delaying write operations to avoid SSD freezing. Our test results show that our scheme significantly reduces the write operation overheads and freezing overheads, and improves the performance of traditional SSD-RAID-1 scheme by 18 percent, and the response time of the scheme by 38 percent.

• Korean Journal of Cognitive Science
• /
• v.22 no.2
• /
• pp.173-192
• /
• 2011

The visual system applies previously learned contextual knowledge to facilitate the perception and encoding of scenes. When extrapolation following the employment of contextual information occurs, it sometimes leads to scene memory distortion: people report as if they saw more than they actually had seen. This phenomenon is called the "boundary extension" effect (Intraub & Richardson, 1989). The present study aimed to clarify the effects of contextual information on boundary extension in a more systematic way. Based on the assumption that it is harder to extract contextual information from inverted scenes compared to intact scenes, we presented inverted scenes either during encoding or retrieval to manipulate the level of contextual information and compared the magnitude of boundary extension effect for upright versus inverted scenes. In a series of experiments, we found that scene inversion during encoding, but not during retrieval, significantly reduced boundary extension. Showing reduced memory distortion for inverted scenes, the current study directly demonstrated that access to contextual information is a critical component of scene extrapolation process.

• Journal of Korea Multimedia Society
• /
• v.12 no.4
• /
• pp.512-520
• /
• 2009

Maximum intensity projection (MIP) is a volume rendering method which extracts maximum values along the viewing direction through volume data. It visualizes high-density structures, such as angio-graphic datasets so that it is frequently used in medical imaging systems. We have proposed an efficient two-step MIP acceleration method that uses the recent CPUs. First, we exploited SIMD instructions to reduce conditional branch instructions which take up a considerable part of whole rendering process, so that we improved rendering speed. Second, we proposed a new method, which accesses volume and image data successively by modifying the shear-warp rendering. This method improves memory access patterns so that cache misses are reduced. Using the current CPUs, our method improved the rendering speed by a factor of 7 than that of the shear-warp rendering.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.1
• /
• pp.101-108
• /
• 2000

The data prefetching scheme is an effective technique to reduce the main memory access latency by exploiting the overlap of processor computations with data accesses. However, if the prefetched data replicate the useful existing data in the cache memory and they are not being used in computations. performances of programs are aggravated. This phenomenon results from the lack of correct predictions for data being used in the future. When parallel programs exploit the data arrays for computations, the grain size is useful information for data prefetching scheme because it implies the range of data using in computations. Based on this information, we suggest a new data prefetching scheme exploited by the grain size of the parallel program. Simulation results show that the suggested prefetching scheme improves the performance of the simulated parallel programs due to the reduction of bus transactions as well as useful prefetching operations.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.2
• /
• pp.57-64
• /
• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• Journal of Broadcast Engineering
• /
• v.21 no.6
• /
• pp.944-956
• /
• 2016

In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.