• Journal of Digital Convergence
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• v.11 no.2
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• pp.287-297
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• 2013

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient "In-place" memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

• Journal of Advanced Marine Engineering and Technology
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• v.29 no.6
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• pp.707-712
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• 2005

PRAM (Phase change random access memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change materials have been researched in the field of optical data storage media. Among the phase change materials. $Ge_2Sb_2Te_5$ is very well known for its high optical contrast in the state of amorphous and crystalline. However the characteristics required in solid state memory are quite different from optical ones. In this study. the structural Properties of GeSbTe thin films with composition were investigated for PRAM. The 100-nm thick $Ge_2Sb_2Te_5$ and $Sb_2Te_3$ films were deposited on $SiO_2/Si$ substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films. x-ray diffraction (XRD). atomic force microscopy (AFM), differential scanning calorimetry (DSC) and 4-point measurement analysis were performed. XRD and DSC analysis result of GST thin films indicated that the crystallization of $Se_2Sb_2Te_5$ films start at about $180^{\circ}C$ and $Sb_2Te_3$ films Start at about $125^{\circ}C$.

• The Journal of Society for e-Business Studies
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• v.14 no.4
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• pp.119-131
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• 2009

During a decade, e-Commerce environments supporting real-time transaction processing have been getting larger. In telecommunication and financial environments, research and building for main memory database systems have been doing to support real-time transaction processing. A research on indexing for fast transaction support focuses on reducing cache misses or reducing memory access latency when cache misses happen. In the paper, we propose a prefetch method for tree index structures to reduce memory access latency. We present a prefetch-efficient pCST-tree and show superiority of the proposed tree by experiments.

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.147-153
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• 2007

This paper represents an analog predistortion linearizer for the high power amplifier with low memory effect. The high power amplifier is implemented using a 90-W peak envelope power(PEP) LDMOSFET at 2.14-GHz and an envelope short matching topology is applied at the active ports to minimize the memory effect. The analog predistortion circuit comprises the fundamental path and the cuber and quintic generating circuits, whose amplitudes and phases can be controlled independently. The predistortion circuit is tested for two-tone and wide-band code division multiple access(WCDMA) 4FA signals. For the WCDMA signal, the adjacent channel leakage ratios(ACLRs) at 5 MHz offset are improved by 12.4 dB at average output powers of 36 dBm and 42 dBm.

• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.589-598
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• 2006

In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.117-123
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• 2013

By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

• Journal of Advanced Marine Engineering and Technology
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• v.31 no.4
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• pp.410-416
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• 2007

PRAM (Phase change random access memory) is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to change the heater electrode material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of heater electrode material parameters using finite element analysis. From the simulation. the reset current of PRAM cell is reduced from 2.0 mA to 0.72 mA as the electrical conductivity of heater is decreased from $1.0{\times}10^6\;(1/{\Omega}{\cdot}m$) to $1.0{\times}10^4\;(1/{\Omega}{\cdot}m$). As the thermal conductivity of heater is decreased, the reset current is slightly reduced. But the reset current of PRAM cell is not changed as the specific heat of heater is changed.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.250-257
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• 2003

As the memory access time becomes slower relative to the fast processor speed, most systems use cache memory to reduce the gap. The cache performance has an increasingly large impact on the performance of algorithms. Blocking is the well known method to utilize cache and has shown good results in multiplying matrices and search trees like d-heap. But if we use blocking in the data structures which require rotation during insertion or deletion, the execution time increases as the data movements between blocks are necessary. In this paper, we have proposed the extended pairing heap algorithms using block node and shown by experiments that our structure is superior Also in case of using block node, we use less memory space as the number of pointers decreases.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.9
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• pp.685-689
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• 2009

Flash memory has several features such as low~power consumption and fast access so that there has been various research on using flash memory as new storage. Especially the Solid State Disk which is composed of flash memory chips has recently replaced the hard disk. At present, SSD adopts the multi-channel and multi-way architecture to exploit advantages of parallel access. In this architecture, data are written on SSD in a unit of a superblock which is composed of multiple blocks in which some blocks are put together. This paper proposes two schemes of selecting, segmenting and re-composing victim superblocks to optimize concurrent processing when a buffer flush occurs. The experimental results show that 35% of superblock- based write operations is reduced by selecting victims and additional 9% by composition of superblock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.425-427
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• 2009

CDMA has been used widely in communication standards like IS-95, WCDMA, and Korea-Japan Satellite-DMB. Since CDMA has a multiple access interference (MAI) problem, a CDMA receiver requires an interference cancellation scheme like prefilter, a kind of adaptive filter. This paper proposed a memory-based prefilter architecture to reduce the area of a prefilter. An adaptive filter is usually implemented with registers for area reduction, but memory-based architecture leads to a less area for a prefilter due to its functional characteristics. Experimental results show that memory-based architecture reduces the area by around 10% in common prefilters.