• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.188-193
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• 2022

The energy efficiency of memory systems is an important task in designing future computer systems as memory capacity continues to increase to accommodate the growing big data. In this article, we present an energy-efficient last-level cache management policy for future mobile systems. The proposed policy makes use of low-power PCM (phase-change memory) as the main memory medium, and reduces the amount of data written to PCM, thereby saving memory energy consumptions. To do so, the policy keeps track of the modified cache lines within each cache block, and replaces the last-level cache block that incurs the smallest PCM writing upon cache replacement requests. Also, the policy considers the access bit of cache blocks along with the cache line modifications in order not to degrade the cache hit ratio. Simulation experiments using SPEC benchmarks show that the proposed policy reduces the power consumption of PCM memory by 22.7% on average without degrading performances.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1947-1954
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• 2011

There are various attacks such as tampering, bypassing and spoofing which are caused with system-wide vulnerabilities of Windows operating system. The underlying operating system is responsible for protecting application-space mechanisms against such attacks. This paper provides the implementation of mandatory access control known as multi-level security (MLS) rating with TCSEC-B1 level on th kernel of Windows$^{TM}$. By adding especially the protection feature against tampering memory of processes to the security kernel, this implementation meets the responsibility against system-wide vulnerabilities.

• Journal of Computing Science and Engineering
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• v.9 no.1
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• pp.1-8
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• 2015

Accessing and searching in a sequence of numbers are fundamental operations in computing that are encountered in a wide range of applications. One of the applications of the problem is cryptanalytic time-memory tradeoff which is aimed at a one-way function. A rainbow table, which is a common method for the time-memory tradeoff, contains elements from an input domain of a hash function that are normally sorted integers. In this paper, we present a practical indexing method for a monotonically increasing static sequence of numbers where the access and search queries can be addressed efficiently in terms of both time and space complexity. For a sequence of n numbers from a universe $U=\{0,{\ldots},m-1\}$, our data structure requires n lg(m/n) + O(n) bits with constant average running time for both access and search queries. We also give an analysis of the time and space complexities of the data structure, supported by experiments with rainbow tables.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.82-88
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• 2014

We study the effect of mesh reordering on Laplacian smoothing for parallel high performance computing systems. Specifically, we use the Reverse-Cuthill McKee algorithm to reorder meshes and use Laplacian Smoothing to improve the mesh quality on Nonuniform memory access architecture-based parallel high performance computing systems. First, we investigate the effect of using mesh reordering on Laplacian smoothing for a single core system and extend the idea to NUMA-based high performance computing systems.

• The KIPS Transactions:PartD
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• v.13D no.6 s.109
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• pp.833-838
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• 2006

Program Plagiarism is an infringement of software copyright. In detecting program plagiarism, many different source program comparison methods has been studied. But, it is not easy to detect plagiarized program that made a few cosmetic changes in program structures and variable names In this paper, we propose a new ground-breaking technique in detecting plagiarism by Memory Access Log Analysis.

• Applied Microscopy
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• v.42 no.4
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• pp.207-211
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• 2012

We examined the electrical properties and microstructure of NiO produced using a sol-gel method and Ni nitrate hexahydrate ($Ni[NO_3]_2{\cdot}6H_2O$) to investigate if this NiO thin film can be used as an insulator layer for resistance random access memory (ReRAM) devices. It was found that as-prepared NiO film was polycrystalline and presented as the nonstoichiometric compound $Ni_{1+x}O$ with Ni interstitials (oxygen vacancies). Resistances-witching behavior was observed in the range of 0~2 V, and the low-resistance state and high-resistance state were clearly distinguishable (${\sim}10^3$ orders). It was also demonstrated that NiO could be patterned directly by KrF eximer laser irradiation using a shadow mask. NiO thin film fabricated by the sol-gel method does not require any photoresist or vacuum processes, and therefore has potential for application as an insulating layer in low-cost ReRAM devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.168-168
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• 2011

정보화 사회가 도래함으로 개인별 정보 이용량이 급격히 증가하였고 스마트폰과 같은 모바일 기기의 개발로 정보 이용량이 최고치를 갱신 중이다. 이러한 흐름 속에 사람들은 빠른 처리 속도와 고도의 저장 능력을 요구하게 되고 이에 따라 새로운 Random Access Memory에 대한 연구가 활발히 진행되고 있다. 현재 Dynamic Random Access Memory (DRAM)가 눈부신 발전과 성과를 이룩하고 있지만 전원 공급이 중단 될 경우 저장된 내용들이 지워진다는 단점을 가지고 있다. DRAM의 장점에 이러한 단점을 보완할 수 있는 차세대 반도체 소자로 주목 받고 있는 것이 Magnetic Random Access Memory (MRAM)이다. DRAM에서 Capacitor와 유사한 기능을 하는 MTJ stack은 tunneling magnetoresistance (TMR) 현상을 나타내는 자기저항 박막을 이용하여 MRAM 소자에 집적된다. 본 연구에서는 MRAM의 자성 재료로 구성된 MTJ stack을 효과적으로 식각하고 우수한 식각 profile을 얻는 동시에 재증착의 문제를 해결하는데 목적을 둔다. 본 IrMn 자성 박막의 식각 연구는 유도결합 플라즈마 반응성 이온 식각 (Inductively Coupled Plasma Reactive Ion Etching: ICPRIE)법을 이용하여 진행되었다. 특히 본 연구에서는 종래의 $Cl_2$, $BCl_3$ 그리고 HBr과 같은 부식성 가스가 아닌 부식성이 없는 $CH_4$가스를 선택하여 그 농도를 변화시키면서 식각하였고 더 나아가 $O_2$를 첨가하면서 그 효과를 극대화하려고 시도하였다. IrMn 자성 박막의 식각 속도, TiN 하드 마스크에 대한 식각 선택도 그리고 profile 등이 조사되었고 최종적으로 X-ray photoelectron spectroscopy (XPS)를 이용하여 식각 메카니즘을 이해하려고 하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.115-117
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• 2022

The electrical characteristics of the monolithic 3-dimensional static random access memory consisting of a feedback field-effect transistor (M3D-SRAM-FBFET) was investigated using technology computer-aided design (TCAD). The N-type FBFET and N-type MOSFET are designed with fully depleted silicon on insulator (FDSOI), and those are located at bottom and top tiers, respectively. For the M3D-SRAM-FBFET, as the supply voltage decreased from 1.9 V to 1.6 V, the reading on-current decreased approximately 10 times.