• The KIPS Transactions:PartA
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• 제11A권7호
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• pp.489-498
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• 2004

VLIW processor is considered to be an appropriate processor for the embedded system, provided with high performance and low power con-sumption due to its simple hardware structure. Unfortunately, the VLIW processor often suffers from high memory access latency due to the variable length of I-packets, which consist of independent instructions to be issued in parallel. It is because of the variable I-packet length that some I-packets must be placed over two cache blocks, which are called straddle I-packets, so that two cache accesses are required to fetch such I-packets. In this paper, an expansion buffer cache is proposed to improve not only the instruction fetch bandwidth, but also the power consumption of the I-cache with moderate hardware cost. The expansion buffer cache has a small expansion buffer containing a fraction of a straddle packet along with the main cache to reduce the additional cache accesses due to the straddle I-packets. With a great reduction in the cache accesses due to the straddle packets, the expansion buffer cache can achieve $5{\~}9{\%}$improvement over the conventional I-caches in the $Delay{\cdot}Power{\cdot}Area$ metric.

• The KIPS Transactions:PartD
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• 제11D권1호
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• pp.51-60
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• 2004

In open GIS environment, a GIS client can access spatial data in different types of GIS sowers with the same Interfaces. This means that open GIS components software ensures the interoperability throughout the heterogeneous GIS servers. The user response time, however, tends to be increased, if the client makes use of the standard interfaces for data accesses that can ensure interoperability. This is because the format of spatial data accessed from a specific GIS server must be transformed into common format, such as Rowset in OLE/DB, which is compatible with the standard interfaces. In this paper, we develop efficient techniques for data buffering in GIS client to reduce the response time. We design the buffer management method, which Is based on the space partitioning, and Integrate buffer management components into MapBase, an open GIS component software. And we also, show that buffer management proposed in this paper yields significant performance improvement in GIS client.

• Proceedings of the Technology Innovation Conference
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• 기술경영경제학회 2003년도 제22회 동계학술발표회 논문집
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• pp.173-190
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• 2003

Demand forecasting is essential in establishing national and corporate strategy as well as the management of their resource. We forecast demand for multi-generation product using discrete choice model combining diffusion model The discrete choice model generally captures consumers'valuation of the product's qualify in the framework of a cross-sectional analysis. We incorporate diffusion effects into a discrete choice model in order to capture the dynamics of demand for multi-generation products. As an empirical application, we forecast demand for worldwide DRAM (dynamic random access memory) and each of its generations from 1999 to 2005. In so doing, we use the method of 'Technological Forecasting'for DRAM Density and Price of the generations based on the Moore's law and learning by doing, respectively. Since we perform our analysis at the market level, we adopt the inversion routine in using the discrete choice model and find that our model performs well in explaining the current market situation, and also in forecasting new product diffusion in multi-generation product markets.

• Journal of KIISE:Computer Systems and Theory
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• 제37권5호
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• pp.304-313
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• 2010

There are several methods for malware analyses. However, it is difficult to detect malware exactly with existing detection methods. Especially, malware with strong anti-debugging facilities can detect analyzer and disturb their analyses. Furthermore, it takes too much time to analyze malware. In order to resolve these problems of current analyzers, more improved analysis scheme is required. This paper suggests a dynamic binary instrumentation which supports the instruction analysis and the memory access tracing. Additionally, by supporting the API call tracing with the DLL loading analysis, our system establishes the foundation for analyzing various executable codes. Based on Xen, full-virtualization environment is built using Intel's VT technology. Windows XP can be used as a guest. We analyze representative malware using several functions of our system, and show the accuracy and efficiency enhancements in binary analyses capability of our system.

• Journal of KIISE
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• 제41권9호
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• pp.611-616
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• 2014

Rabin fingerprinting used for chunking requires the largest amount computation time in data deduplication, In this paper, therefore, we proposed parallel Rabin fingerprinting on GPGPU for efficient data deduplication. In addition, for efficient parallelism in Rabin fingerprinting, four issues are considered. Firstly, when dividing input data stream into data sections, we consider the data located near the boundaries between data sections to calculate Rabin fingerprint continuously. Secondly, we consider exploiting the characteristics of Rabin fingerprinting for efficient operation. Thirdly, we consider the chunk boundaries which can be changed compared to sequential Rabin fingerprinting when adapting parallel Rabin fingerprinting. Finally, we consider optimizing GPGPU memory access. Parallel Rabin fingerprinting on GPGPU shows 16 times and 5.3 times better performance compared to sequential Rabin fingerprinting on CPU and compared to parallel Rabin fingerprinting on CPU, respectively. These throughput improvement of Rabin fingerprinting can lead to total performance improvement of data deduplication.

• Journal of the Korea Computer Industry Society
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• 제6권5호
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of Korea Multimedia Society
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• 제10권11호
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• pp.1446-1459
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• 2007

This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.

• Journal of KIISE:Software and Applications
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• 제30권7_8호
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• pp.610-617
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• 2003

Similarity matching in video database is of growing importance in many new applications such as video clustering and digital video libraries. In order to provide efficient access to relevant data in large databases, there have been many research efforts in video indexing with diverse spatial and temporal features. however, most of the previous works relied on sequential matching methods or memory-based inverted file techniques, thus making them unsuitable for a large volume of video databases. In order to resolve this problem, this paper proposes an effective and scalable indexing technique using a trie, originally proposed for string matching, as an index structure. For building an index, we convert each frame into a symbol sequence using a window order heuristic and build a disk-resident trie from a set of symbol sequences. For query processing, we perform a depth-first search on the trie and execute a temporal segmentation. To verify the superiority of our approach, we perform several experiments with real and synthetic data sets. The results reveal that our approach consistently outperforms the sequential scan method, and the performance gain is maintained even with a large volume of video databases.

• Journal of Advanced Navigation Technology
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• 제20권1호
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• pp.79-85
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• 2016

Network traffic is increased rapidly, due to mobile and social network, such as smartphones and facebook, in recent web environment. In this paper, we improved web response time of existing system using direct buffer of NIO and DMA. This solved the disadvantage of JAVA, such as CPU performance reduction due to the blocking of I/O, garbage collection of buffer. Key values circulated many data due to priority change put on a hash map operated easily and apply a priority modification algorithm. Large response data is separated and stored at a fast direct buffer and improved performance. This paper showed that the proposed method using NIO was much improved performance, in many test situations of cache hit and cache miss.

• The Transactions of the Korea Information Processing Society
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• 제6권4호
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• pp.841-850
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• 1999

Many commercial database systems maintain histograms to summarize the contents of relations, permit efficient estimation of query result sizes, and access plan costs. In spatial database systems, most query predicates consist of topological relationship between spatial objects, and ti is ver important to estimate the selectivity of those predicates for spatial query optimizer. In this paper, we propose a selectivity estimation scheme for spatial topological predicates based on the multi-dimensional histogram and the transformation scheme. Proposed scheme applies two partition strategies on transformed object space to generate spatial histogram, and estimates the selectivity of topological predicates based on the topological characteristic of transformed space. Proposed scheme provides a way for estimating the selectivity without too much memory space usage and additional I/Os in spatial query optimizer.