• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.7
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• pp.668-679
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• 1990

The fully digitalized inveter has some difficulties in implementation because of the limitation of available memory capacity and computation time. This paper describes a new PWM(Pulse Width Modulation) Inverter technique which linearizes switching angle characteristics of SHEPWM(Selected Harmonic Eliminatin Pulse Width Modulation) Inverter. Also the detailed description of the scheme along with the realization is presented. The simulation and experimental results show that the proposed schemes have the advantates such as good voltage waveforms and memory-saving.

• Proceedings of the SAREK Conference
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• 2003.07a
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• pp.92-92
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• 2003

• The Journal of Society for e-Business Studies
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• v.8 no.3
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• pp.165-176
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• 2003

Instead of existing cell phones, PDAs are observed as leading wireless Internet devices recently Numerous applications are developed by extended usage of PDAs and it should be installed appropriately according to devices. Furthermore, when battery is discharged, all data stored in RAM(Random Access Memory) becomes obsolete. So it should be recovered or reinstalled from flash memory, backup media or something. In this paper, we present an automatic application installation system(PAIS : PDA Automatic Installation System) to solve problems that users have to install applications by themselves whenever it is necessary. With this system, users feel comfortable by saving time and effort to install each applications and application development companies save cost needed to make materials illustrating installation process. Consequently PAIS may flourish wireless Internet business.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.249-255
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• 2007

In general, a large amount of the memory accesses are required for the CAVLC decoding in H.264/AVC. It is a serious problem for the applications such as a DMB and videophone services because the considerable power is consumed for accessing the memory. In order to solve this problem, we propose an efficient decoding method for the coeff-token which is one of the syntax elements of CAVLC. In this paper, the variable length code table is re-designed with the new codewords which are defined by investigating the architecture of the conventional codeword for the coeff_token element. A new coeff_token decoding method is developed based on the suggested table. The simulation results show that the proposed algorithm achieves an approximately 85% memory access saving without video-quality degradation, compared to the conventional CAVLC decoding.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.68-74
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm can obtain around 1.7% BD-bitrate gain and 0.03dB BD-PSNR gain, compared with the conventional fixed-bit min-max algorithm with 37.5% memory saving.

• Nuclear Engineering and Technology
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• v.48 no.3
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• pp.635-641
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• 2016

Because of prohibitive data storage requirements in large-scale simulations, the memory problem is an obstacle for Monte Carlo (MC) codes in accomplishing pin-wise three-dimensional (3D) full-core calculations, particularly for whole-core depletion analyses. Various kinds of data are evaluated and quantificational total memory requirements are analyzed based on the Reactor Monte Carlo (RMC) code, showing that tally data, material data, and isotope densities in depletion are three major parts of memory storage. The domain decomposition method is investigated as a means of saving memory, by dividing spatial geometry into domains that are simulated separately by parallel processors. For the validity of particle tracking during transport simulations, particles need to be communicated between domains. In consideration of efficiency, an asynchronous particle communication algorithm is designed and implemented. Furthermore, we couple the domain decomposition method with MC burnup process, under a strategy of utilizing consistent domain partition in both transport and depletion modules. A numerical test of 3D full-core burnup calculations is carried out, indicating that the RMC code, with the domain decomposition method, is capable of pin-wise full-core burnup calculations with millions of depletion regions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1074-1079
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• 2004

So far, many sensors such as a structured grid pattern generator, a laser, and CCD camera to obtain 3D information have been used, but most of algorithms for a calibration are inefficient since a huge memory and experiment time are required. In this paper, the calibration algorithm of a structured grid pattern based on triangulation method is introduced to calculate 3D information in the real world. The beams generated from structured grid pattern generator established horizontally with the CCD camera are projected on the calibration plat. A CCD camera measures the intersection plane of a projected beam and an object plane. The 3D information is calculated using measured and calibration datum. This proposed method in this paper has advantages such as a memory saving and an efficient experimental time since the 3D information is obtained simply the triangulation method.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.1
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• pp.1-7
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• 2012

A Smartphone has an ability accessing Internet by URL stored in NFC(Near Field Communication) Tag for storing the information of items, blogs and web pages. Because the system works through the Internet with URL, however, it needs to pay some costs like communication fee and time. If we can store the web page on the tags, we can save the communication overhead. But they have too small memory to store it. In this paper, we introduce the Micro-Webpage technology which can be stored in NFC tag or QR(Quick Response) code. To make a Micro-Webpage, we remove control tags from the web page to leave a user original content. The removed control tags are stored in our smartphone application as a template. The user content is also compressed to a smaller one by an lossless compression algorithm. When a tag is read, the stored content is decompressed and, it is combined with the template to make the original web page. We have implemented a prototype of Micro-Webpage system on Android platform and confirmed that the prototype has reasonable performance improvements in saving memory and loading web page time.

• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.207-224
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• 2010

This paper presents a compression scheme for mesh geometry, which is suitable for mobile graphics. The main focus is to enable real-time decoding of compressed vertex positions while providing reasonable compression ratios. Our scheme is based on local quantization of vertex positions with mesh partitioning. To prevent visual seams along the partitioning boundaries, we constrain the locally quantized cells of all mesh partitions to have the same size and aligned local axes. We propose a mesh partitioning algorithm to minimize the size of locally quantized cells, which relates to the distortion of a restored mesh. Vertex coordinates are stored in main memory and transmitted to graphics hardware for rendering in the quantized form, saving memory space and system bus bandwidth. Decoding operation is combined with model geometry transformation, and the only overhead to restore vertex positions is one matrix multiplication for each mesh partition. In our experiments, a 32-bit floating point vertex coordinate is quantized into an 8-bit integer, which is the smallest data size supported in a mobile graphics library. With this setting, the distortions of the restored meshes are comparable to 11-bit global quantization of vertex coordinates. We also apply the proposed approach to compression of vertex attributes, such as vertex normals and texture coordinates, and show that gains similar to vertex geometry can be obtained through local quantization with mesh partitioning.

• Electrical & Electronic Materials
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• v.10 no.4
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• pp.349-354
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• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.