• The Transactions of the Korea Information Processing Society
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• v.13 no.3
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• pp.91-101
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• 2024

The utilization of container virtualization technology ensures the consistency and portability of data-intensive and memory volatile workflows. Kubernetes serves as the de facto standard for orchestrating these container applications. Cloud users often overprovision container applications to avoid container restarts caused by resource shortages. However, overprovisioning results in decreased CPU and memory resource utilization. To address this issue, oversubscription of container resources is commonly employed, although excessive oversubscription of memory resources can lead to a cascade of container restarts due to node memory scarcity. Container restarts can reset operations and impose substantial overhead on containers with high memory volatility that include numerous stateful applications. This paper proposes a technique to mitigate container restarts in a memory oversubscription environment based on Kubernetes. The proposed technique involves identifying containers that are likely to request memory allocation on nodes experiencing high memory usage and temporarily pausing these containers. By significantly reducing the CPU usage of containers, an effect similar to a paused state is achieved. The suspension of the identified containers is released once it is determined that the corresponding node's memory usage has been reduced. The average number of container restarts was reduced by an average of 40% and a maximum of 58% when executing a high memory volatile workflow in a Kubernetes environment with the proposed method compared to its absence. Furthermore, the total execution time of a container workflow is decreased by an average of 7% and a maximum of 13% due to the reduced frequency of container restarts.

• Archives of design research
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• v.13
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• pp.15-24
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• 1996

No mater how brilliant brain a man has, as time goes by, it is certain to fall into a lapse of memory phenomenon in according to cease to exist as a matter of course. But as previously stated, there is no room for douby, if we make advertising information for being changed into a sign which is to be treated easily and simplified, we can easily memory and withdraw it. In other words, the information is to be coded simpler, the memory and recollection of it is to be easier as wll as we can raise the precision rate. Good many advertising today, it appears, try to raise the acknowlegement rate with shock of good-sized and exposure frequency. In this advertising form, we can aspire to the intention of advertiser to try to get lapse of the message of advertising. Of course, even if it cannot be an index of every advertising information called simplified memory and recollection rate, it should be emphasized that it cannot but have something to do with the consumer's memory. Which to be obtained by invested advertisement. As for it, there are so many things to be taken charge of a lots of content by graphic designer: to be obtained mental distribution of resources inconnected with a desire of consumer, to be converted memory information into being less than that and treated easier, and to be correlated the memory information with the previously known things.

• Bulletin of Food Technology
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• v.22 no.1
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• pp.51-58
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• 2009

• ETRI Journal
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• v.25 no.3
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• pp.179-186
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• 2003

Using biometrics to verify a person's identity has several advantages over the present practices of personal identification numbers (PINs) and passwords. At the same time, improvements in VLSI technology have recently led to the introduction of smart cards with 32-bit RISC processors. To gain maximum security in verification systems using biometrics, verification as well as storage of the biometric pattern must be done in the smart card. However, because of the limited resources (processing power and memory space) of the smart card, integrating biometrics into it is still an open challenge. In this paper, we propose a fingerprint verification algorithm using a multi-resolution accumulator array that can be executed in restricted environments such as the smart card. We first evaluate both the number of instructions executed and the memory requirement for each step of a typical fingerprint verification algorithm. We then develop a memory-efficient algorithm for the most memory-consuming step (alignment) using a multi-resolution accumulator array. Our experimental results show that the proposed algorithm can reduce the required memory space by a factor of 40 and can be executed in real time in resource-constrained environments without significantly degrading accuracy.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.3
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• pp.487-499
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• 2022

Machine learning such as deep learning have been widely used in recent years. Recently deep learning is performed in a trusted execution environment such as ARM TrustZone to improve security in edge devices and embedded devices with low computing resource. To mitigate this problem, we propose TPMP that efficiently uses the limited memory of TEE through DNN model partitioning. TPMP achieves high confidentiality of DNN by performing DNN models that could not be run with existing memory scheduling methods in TEE through optimized memory scheduling. TPMP required a similar amount of computational resources to previous methodologies.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1200-1208
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• 2003

Java Card technology allows us to run Java applications on smart cards and other memory-constrained devices. Java Card technology supports high security, portability and ability of storing and managing multiple applications. However, constrained memory resources of the Java Card Platform hinder wide deployment of the Java Card applications. Therefore, in this paper we propose a bytecode optimization algorithm to use the memory of a Java Card efficiently. Our algorithm can reduce the size of the bytecode by sharing the memory of the parameters of the catch clause in the try-catch-finally sentence.

• Journal of the Korea Society of Computer and Information
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• v.24 no.4
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• pp.1-9
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• 2019

LRR(Loose Round Robin) warp scheduling policy for GPU architecture results in high warp-level parallelism and balanced loads across multiple warps. However, traditional LRR policy makes multiple warps execute long latency operations at the same time. In cases that no more warps to be issued under long latency, the throughput of GPUs may be degraded significantly. In this paper, we propose a new warp scheduling policy which utilizes latency hiding, leading to more utilized memory resources in high performance GPUs. The proposed warp scheduler prioritizes memory instruction based on GTO(Greedy Then Oldest) policy in order to provide reduced memory stalls. When no warps can execute memory instruction any more, the warp scheduler selects a warp for computation instruction by round robin manner. Furthermore, our proposed technique achieves high performance by using additional information about recently committed warps. According to our experimental results, our proposed technique improves GPU performance by 12.7% and 5.6% over LRR and GTO on average, respectively.

• Journal of information and communication convergence engineering
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• v.19 no.1
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• pp.22-28
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• 2021

Convolutional neural networks (CNNs) are one of the most frequently used artificial intelligence techniques. Among CNN-based applications, small and timing-sensitive applications have emerged, which must be reliable to prevent severe accidents. However, as the small and timing-sensitive systems do not have sufficient system resources, they do not possess proper error protection schemes. In this paper, we propose MATE, which is a low-cost CNN weight error correction technique. Based on the observation that all mantissa bits are not closely related to the accuracy, MATE replaces some mantissa bits in the weight with error correction codes. Therefore, MATE can provide high data protection without requiring additional memory space or modifying the memory architecture. The experimental results demonstrate that MATE retains nearly the same accuracy as the ideal error-free case on erroneous DRAM and has approximately 60% accuracy, even with extremely high bit error rates.

• Geophysics and Geophysical Exploration
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• v.21 no.4
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• pp.213-219
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• 2018

In this study, we simulated 3D wave propagation modeling using a Xeon Phi x200 processor and compared the parallel computation performance with that using a Xeon CPU. Unlike the 1st generation Xeon Phi coprocessor codenamed Knights Corner, the 2nd generation x200 Xeon Phi processor requires no additional communication between the internal memory and the main memory since it can run an operating system directly. The Xeon Phi x200 processor can run large-scale computation independently, with the large main memory and the high-bandwidth memory. For comparison of parallel computation, we performed the modeling using the MPI (Message Passing Interface) and OpenMP (Open Multi-Processing) libraries. Numerical examples using the SEG/EAGE salt model demonstrated that we can achieve 2.69 to 3.24 times faster modeling performance using the Xeon Phi with a large number of computational cores and high-bandwidth memory compared to that using the 12-core CPU.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.