• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 추계학술대회 논문집
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• pp.955-958
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• 2000

In this paper, the electro-chemical-machining characteristics of Ni-Ti Shape Memory Alloy(SMA) was investigated. From the experimental results, the optimal electro chemical machining conditions for satisfying the machining quality(fine surface & high recovery stress)might be confirmed. And it was concluded that optical electro chemical condition for Ni-Ti SMA could be obtained at approximately 100% current efficiency and high frequency pulse current.

• 조명전기설비학회논문지
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• 제24권5호
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• pp.55-61
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• 2010

PLC 제어 시스템은 SFC 언어를 사용하여 설계할 경우, SFC 언어를 사용하면 제어의 흐름을 이해하기 쉽고, 유지보수가 용이하며 프로그램의 기술성이 뛰어나다. SFC 언어는 단일 시퀀스, 선택 시퀀스, 병렬 시퀀스로 나누어지며, 선택 시퀀스로 프로그래밍 하면 단일 시퀀스로 프로그램할 때보다 메모리의 크기가 커져야 한다. 본 논문에서는 선택 시퀀스의 기능을 단일 시퀀스로 구현하여 메모리의 크기를 줄여서 메모리의 효율을 향상시키는 방법을 제시하고, 실례를 통해 타당성을 확인하였다.

• 한국산학기술학회논문지
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• 제7권2호
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• pp.126-130
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• 2006

PLC는 산업용 제어시스템에서 널리 사용되고 있으며, 중요한 역할을 하고 있다. PLC에서 사용되는 언어중 SFC는 이산 제어 프로그램에서 순차제어 논리의 기술에 적합한 그래픽 언어이며, SFC로 공정제어 시스템을 구현할 때는 분산제어 구조와 계층제어 구조로 구현하게 된다. 계층제어 구조에서는 서브시스템 간에 동기를 맞추기 위해서 서브시스템은 별도로 구성하고 동기신호만을 주고받게 된다. 그러면 메모리 효율 및 시스템 성능이 좋지 않게 된다. 본 논문에서는 계층제어 구조에서 메모리 효율을 향상시키는 방법을 제안하였고, 실례를 통해 그의 타당성을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권4호
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• pp.1922-1940
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• 2019

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제22권10호
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• pp.513-520
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• 2016

IoT 기기가 대중들에게 보급화 됨에 따라서 임베디드 시스템의 성능뿐만 아니라 소모하는 에너지에 관한 문제가 중요하게 대두되고 있다. 이는 특히 휴대용 임베디드 기기에서 더 중요한데, 휴대용 임베디드 기기들은 각 디바이스들이 가지고 있는 배터리를 통하여 전원을 얻기 때문에 얼마나 효율적으로 잘 사용하는지가 곧 시스템의 사용시간으로 귀결되기 때문이다. 본 논문에서는 임베디드 리눅스 시스템에서의 에너지 소모량을 줄이기 위하여 디바이스의 frequency를 조절해주는 주파수 변경 프레임 워크를 통하여 최고의 에너지 효율을 갖는 메모리 frequency를 찾고, 메모리 총 사용량을 통한 새로운 디바이스 주파수 변경 기법을 제안한다. 실험을 통해 본 논문에서 제안하는 정책은 이전의 정책과 비교하여 최악의 경우에도 나쁜 에너지 효율을 보이지 않으며 최대 18%의 에너지 감소율을 보였다.

• 전자공학회논문지B
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• 제28B권9호
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• pp.703-711
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• 1991

In this paper, an efficient storage reclamation algorithm for RISC parallel processing in the object orented programming environments is presented. The memory management for the dynamic memory allocation and the frequent memory access in object oriented programming is the main factor that decreases RISC parallel processing performance. The proposed algorithm can be efficiently allocated the memory space of RISCy computer which is required the frequent memory access, so it can be increased RISC parallel processing performance. The proposed algorithm is verified the efficiency by implementing C language on SUN SPARC(4.3 BSD UNIX).

• 대한임베디드공학회논문지
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• 제10권6호
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• pp.391-397
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• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2000년도 추계학술대회논문집 - 한국공작기계학회
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• pp.320-325
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• 2000

This study was performed to investigate the electro-chemical-machining (ECM) characteristic of Ni-Ti Shape Memory Alloy (SMA). From the experimental results, we could gain optimal electro-chemical conditions to bound with lesser machining effect and better surface roughness than any other machining methods to workpiece at the same time. At these conditions, current efficiency was, for especially ECM working of Ni-Ti SMA, approximately 100% and high frequency pulse current was detected.

• 한국전기전자재료학회논문지
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• 제35권5호
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2011년 춘계학술대회논문집
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.