• 전자공학회논문지C
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• 제36C권8호
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• pp.22-34
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• 1999

본 논문에서는 내장된 이중-포트 메모리를 위한 효율적인 테스트 알고리듬을 제안하였다. 제안된 테스트 알고리듬은 기존의 멀티-포트 메모리 테스트 알고리듬들보다 훨씬 빠르게 이중-포트 메모리를 테스트할 수 있으며, 고착 고장, 천이 고장 및 결합 고장을 완벽하게 검출할 수 있다. 또한, 본 연구에서는 제안된 알고리듬을 수행할 수 있는 BIST 회로를 Verilog-HDL을 이용하여 설계하고 시뮬레이션과 합성을 수행하였으며, BIST로 구현된 제안된 테스트 알고리듬의 높은 효율성을 다양한 크기의 내장 메모리에 대한 실험을 통하여 확인할 수 있었다.

• 전자공학회논문지C
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• 제35C권8호
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• pp.10-22
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• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

• 전자공학회논문지C
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• 제35C권8호
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• 한국통신학회논문지
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• 제22권7호
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• 대한전자공학회논문지
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• 제27권5호
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• pp.699-708
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• 1990

This paper proposes two test procedures for detecting functional faults in semiconductor random access memories (RAM's) and a new testimg scheme to execute the proposed test procedures. The first test procedure detects stuck-at faults, coupling faults and decoder faults, and requires 19N operations, which is an improvement over conventional procedures. The second detects restricted patternsensitive faults and requires 69N operations. The proposed scheme uses Built-In Self Testing (BIST) techniques. The scheme can write into more memory cells than I/O pins can in a write cycle in test mode. By using the scheme, the number of write operations is reduced and then much testing time is saved.