• The Journal of Korean Academy of Prosthodontics
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• v.37 no.6
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• pp.791-799
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• 1999

The purpose of this study was to investigate the displacements of cast framework by torch soldering and electric soldering techniques. Specimen had two cylinders and connecting bar that had sectioned with 0.3mm gap at mid point. 10 of total specimens were divided into two groups. In torch soldered group, soldering investment block was made and conventional torch solder-ing procedure was carried out. In electric soldered group, electric soldering was carried out on the master cast without soldering investment block by using electric soldering machine(Dentapunkt DP 7, Kulzer, Germany) After soldering procedure, three dimensional coordinates of two centroids of each cylinder were measured by three dimensional coordinate measuring machine. The intercentroidal displacement and global displacement were calculated and then, these values were compared and evaluated. The results were obtained as follows: 1. Intercentroidal distances of specimens decreased after both soldering procedures, and the decrease in intercentroidal distance was greater for torch soldered group than for electric soldered group 2. Global displacements of torch soldered group were greater than those of electric soldered group.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1207-1216
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• 2020

Since the server system in the cloud environments can simultaneously operate multiple OS and commonly share the memory space between users, an adversary can recover some secret information using cache side-channel attacks. In this paper, the Flush+Reload attack, a kind of cache side-channel attacks, is applied to the optimized precomputation table implementation of Korea block cipher standard ARIA. As an experimental result of attack on ARIA-128 implemented in Ubuntu environment, we show that the adversary can extract the 16 bytes last round key through Flush+Reload attack. Furthermore, the master key of ARIA can be revealed from last and first round key used in an encryption processing.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1059-1070
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• 2018

The block cipher Zorro is designed to reduce the implementation cost for side-channel countermeasure. It has a structure similar to AES, but the number of S-Boxes used is small. However, since the master key is used as the round key, it can be vulnerable to related key attacks. In this paper, we show key recovery attacks on Zorro using related-key differential characteristics. In addition, the related key differential characteristics are fatal when Zorro is used as the base block cipher of the hash function. In this paper, we describe how these characteristics can be linked to collision attacks in the PGV models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korean Operations Research and Management Science Society
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• v.12 no.2
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• pp.42-50
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• 1987

This objective of this paper is to develop an efficient method with small memory requirement for a feed-mixing problem on a micro computer. First this method uses the decomposition principle to reduce the memory requirement. Next, the decomposition principle is modified to fit the problem. Further four different variations in solving subproblems are designed in order to improve efficiency of the principle. According to the test with respect to the processing time, the best variation is such that the dual simplex method is used, and the optimal basis of a previous subproblem is used as an initial basis, and the master problem is (M +1) dimensional. In general, the convergence of solution becomes slower near the optimal value. This paper introduces a termination criterion for a sufficiently good solution. According to the test, 5%-tolerence is acceptable with respect to the relation between the processing time and optimal value.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.767-770
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• 2000

A novel process is newly developed for building RP(Rapid Prototyping) parts using a sheet lamination technique. The build process of existing sheet lamination type RP machines consists of the following steps : feeding, lamination and cutting. In this process, the laminated part of an object is often scratched by a cutter or damaged by a laser beam due to the cutting operation preceded by lamination, In addition, decubing of the unused portion from the laminated block is difficult. In the new process, cutting operation is performed before lamination. The cutting operation takes place while a paper sheet is firmly attached on the plate using electrostatic force. Then liquid glue is applied to the calculated region of the given contour for lamination. The process aims to manufacture a $2k RP machine, what we call the Freeform Mater I, that can use A4 or latter-size used papers. A prototype machine that demonstrates the design concept is built and further research issues are discussed.

• Journal of the Korean institute of surface engineering
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• v.37 no.1
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• pp.22-27
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• 2004

Copper electroforming process has been applied to duplicate Koryo Tripitaka (Taejang'kyong), wooden printing block. Thin copper replica printing plates of 1 mm thickness was successfully manufactured from the printing face (54.5${\times}$25.5 cm) of wooden printing plate. Major processes are (1) silicon rubber replication of the master (2) silvering on silicon rubber (3) copper electroforming (4) separation of copper from the silicon mandrel (5) final coloring by brass plating and trimming. This process has various Potential applications in making thin metallic objects such as plaques, statues, bust and hollow metal objects for jewelry.

• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.337-340
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• 2007

냉간단조금형(Cold Forging Die)의 다이블록(Dieblock)을 제작하는 방법 중의 하나로, 다이블록 제작용 재료를 면가공 하여 다이블록 상면(上面)을 마스터펀치(Master Punch)인 호브(Hob)로 압입(Indentaion) 시켜 절삭가공((Cutting Work)이 아닌 다이호빙(Die Hobbing) 방법으로 임프레션(Impression)을 성형하여 제작하고 있다. 이 방법에 의하여 다이블록의 재료를 합금공구강(Alloy Tool Steel)인 SKD11을 사용하여 제작하고, 스테인리스판(Stainless Sheet Metal)을 제품 재료로 하여 냉간단조가공(Cold Forging Work)을 하였더니 6,000 스트로크(Stroke)에서 금형수명(Die Life)을 다 하였다. 본 논문에서는 다이블록 재료를 고속도공구강(High Speed Tool Steel)인 SKH51로 교체 제작하고, 탄소강(Carbon Steel)인 S45C를 제품 재료로 하여 냉간단조가공을 수행 하였더니 21,000 스트로크에서 금형수명을 다하고 종료 되어 종래의 방법과 비교 검토 하였을 때 350%의 금형수명 연장 효과를 얻게 되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.