• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2005.09a
• /
• pp.147-150
• /
• 2005

We process a novel approach cal led combined nanoimprint and photolithography (CNP) to greatly simplify the fabrication in conventional nanoimprint lithography (NIL). In this study, a novel HMM with anti-sticking $SiO_2$ layer is introduced to improve the quality of transferred pattern. The surface property was investigated using contact angle measurement and spectrophotometer. Replicate pattern with CNP using HMM showed complete pattern transfer without defect.

• Annual Conference of KIPS
• /
• 2020.11a
• /
• pp.807-809
• /
• 2020

기존의 CCTV 관리 체계는 사건·사고에 대한 신속한 조치가 불가능하고 정황 파악이나 증거자료 확보 등 사후조치의 성격이 강하다. 본 논문에서는 Mask R-CNN(Regions with CNN)을 이용하여 CCTV가 읽어 들이는 객체가 응급상황인지 판단하는 방법을 제시한다. 사람으로 인식되는 영역을 다층 퍼셉트론(MLP, Multi-Layer Perceptron)으로 학습시켜 해당 대상이 처한 상황을 인지하고 응급상황으로 인식되는 상황이 지속될 경우 관리 모니터를 통해 사용자에게 알림을 준다. 본 연구를 통해 실시간 상호작용적인 CCTV 관리 체계를 구축하여 도움이 필요한 사람의 골든타임을 놓치지 않게 될 것으로 기대한다.

• Proceedings of the KIEE Conference
• /
• 1995.07c
• /
• pp.1085-1087
• /
• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.9 no.2
• /
• pp.212-216
• /
• 1999

SiC(3C) photodiodes (PDs) were fabricated on p-type Si(111) substrates using chemical vapor deposition (CVD) technique by pyrolyzing tetramethylsilane (TMS) with $H_{2}$ carrier gas. Electrical properties of SiC(3C) were investigated by Hall measurement and current-voltage (I-V) characteristics. SiC(3C) layers exhibited n-type conductivity. Ohmic contact was formed by thermal evaporation Al metal through a shadow-mask. The optical gain $(G_{op})$ of the SiC(3C)/Si PD was measured as a function of the incident wavelength. For the analysis of the photovoltaic detection of the Sic(3C) n/p PD, the spectral response (SR) has calculated by using the electrical parameters of the SiC(3C) layer and the geometric structure of the PD. The peak response calculated for properly chosen parameters was about 0.75 near 550 nm. We expect a good photoresponse in the SiC(3C) heterostructure for the wavelength range of 400~600 nm. The SiC(3C) photodiode can detect blue and near ultraviolet (UV) radiation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.7
• /
• pp.1-6
• /
• 2000

In this study, the effects of the addition of $N_2$ gas into the $Cl_2$ (90)/Ar(10) gas mixture, which has been proposed as the optimized etching gas combination, for etching of platinum was performed. The selectivity of platinum film to $SiO_2$ film etch mask increased with the addition of $N_2$ gas, and etch profile over 75 $^{\circ}$ could be obtained when 20 % additive $N_2$ gas was added. These phenomena were interpreted as the results of a formation of blocking layer such as Si-N or Si-O-N on the $SiO_2$ mask. The maximum etch rate of Pt film and selectivity of Pt to $SiO_2$ are 1425 ${\AA}$/min and 1.71, respectively. These improvements were considered to be due to the formation of more volatile compounds such as Pt-N or Pt-N-Cl.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.162-162
• /
• 2014

최근 들어 wearable computing에 대한 수요가 증가하면서 flexible device에 대한 연구가 활발히 진행되고 있다. 하지만, flexible device를 구현하기 위해서는 기판의 damage를 줄이기 위한 저온공정, device life-time 향상을 위한 passivation, 와이어 본딩 등 다양한 문제들이 해결 되어야 한다. 이러한 문제들 중, polymer 기판과 금속간의 접착력을 향상시키기 위해서 많은 연구자들은 기판의 표면에 adhesive layer를 도포하거나 금속잉크의 solvent를 변화시키는 등의 연구를 진행해왔다. 종래의 연구는 기존 device를 대체 할 수 있을 정도의 생산성과 polymer 기판에 대한 열 적인 손상 이 문제가 되었다. 종래의 문제를 해결하기 위하여 저온공정, in-line system이 가능한 준 준 대기압 플라즈마를 사용하였다. 본 연구에서는 금속잉크를 Ink-jet으로 jetting하여 와이어 본딩 하는 과정에서 전도성 ink의 선폭을 유지시키고 접착력을 향상하기 위하여 준 대기압 플라즈마 공정을 이용하여 이러한 문제점을 해결하고자 하였다. Polymer 기판 표면에 roughness를 만들기 위해 대략 수백 nm 크기를 갖는 graphene flake를 spray coating하여 마스크로 사용하고 준 대기압 플라즈마를 이용하여 표면을 식각 함으로써 roughness를 형성시켰다. 준 대기압 플라즈마를 발생시키기 위해 double discharge system에서 6 slm/1.5 slm (He/O2) gas composition을 하부 전극에 흘려보내고 60 kHz, 5 kV 파워를 인가하였다. 동시에 상부 전극에는 30 kHz, 5 kV 파워를 인가하여 110초 동안 표면 식각 공정을 진행하였다. Graphene flake mask가 coating되어 있는 유연기판을 산소 플라즈마 처리 한 후 물에 3초 동안 세척하여 표면에 남아있는 graphene flake를 제거하고 6 slm/0.3 slm (He/SF6)의 유량으로 주파수와 파워 모두 동일 조건으로 110초 동안 표면 처리를 하였다. Figure 1은 표면 개질 과정과 graphene flake를 mask로 사용하여 얻은 roughness 결과를 SEM을 이용하여 관찰한 결과이다. 이와 같이 실험한 결과 ink와 기판간의 접촉면적을 늘려주고 접촉 각을 조절하여 Wenzel model 을 형성 할 수 있는 표면 roughness를 생성하였고 표면의 화학적 결합을 C-F group으로 치환하여 표면의 물과 접촉각 이 $47^{\circ}$에서 $130^{\circ}$로 증가하는 것을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.788-791
• /
• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Korean Journal of Materials Research
• /
• v.9 no.3
• /
• pp.257-262
• /
• 1999

The selective area growth of GaN by metal organic chemical vapor deposition has been carried out on GaN/ sapphire substrate using $SiO_2$ mask. We investgated the effect of growth parameters such as flow rate of $NH_3$(500­~1300sccm) and the growth temperature(TEX>$950~1060^{\circ}C$) on the growth selectivity and characteristics of GaN using the Scanning Electron Microscopy(SEM). The selectivity of GaN improved as flow rate of NH, and growth temperature in­creased. But the grown GaN shapes on the substrate windows was independent of the flow rate of $NH_3$. On the pattern shapes such as circle, stripe, and radiational pattern(rotate the stripe pattern by $30^{\circ}, 45^{\circ}$), we observed the hexagonal pyramid, the lateral over growth on the mask layer, and the difference of the lateral growth rate depending on growth condition.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.389-390
• /
• 2012

In this study, we fabricate a superhydrophobic surface made of hierarchical nanostructures that combine wax crystalline structure with moth-eye structure using vacuum cluster system and measure their hydrophobicity and durability. Since the lotus effect was found, much work has been done on studying self-cleaning surface for decades. The surface of lotus leaf consists of multi-level layers of micro scale papillose epidermal cells and epicuticular wax crystalloids [1]. This hierarchical structure has superhydrophobic property because the sufficiently rough surface allows air pockets to form easily below the liquid, the so-called Cassie state, so that the relatively small area of water/solid interface makes the energetic cost associated with corresponding water/air interfaces smaller than the energy gained [2]. Various nanostructures have been reported for fabricating the self-cleaning surface but in general, they have the problem of low durability. More than two nanostructures on a surface can be integrated together to increase hydrophobicity and durability of the surface as in the lotus leaf [3,5]. As one of the bio-inspired nanostructures, we introduce a hierarchical nanostructure fabricated with a high vacuum cluster system. A hierarchical nanostructure is a combination of moth-eye structure with an average pitch of 300 nm and height of 700 nm, and the wax crystalline structure with an average width and height of 200 nm. The moth-eye structure is fabricated with deep reactive ion etching (DRIE) process. $SiO_2$ layer is initially deposited on a glass substrate using PECVD in the cluster system. Then, Au seed layer is deposited for a few second using DC sputtering process to provide stochastic mask for etching the underlying $SiO_2$ layer with ICP-RIE so that moth-eye structure can be fabricated. Additionally, n-hexatriacontane paraffin wax ($C_{36}H_{74}$) is deposited on the moth-eye structure in a thermal evaporator and self-recrystallized at $40^{\circ}C$ for 4h [4]. All of steps are conducted utilizing vacuum cluster system to minimize the contamination. The water contact angles are measured by tensiometer. The morphology of the surface is characterized using SEM and AFM and the reflectance is measured by spectrophotometer.

• Journal of the Korean Vacuum Society
• /
• v.22 no.3
• /
• pp.150-155
• /
• 2013

Textured surface has been fabricated to reduce the light reflectance from the solar cells. The textured surface is very suitable for the multi-junction III-V solar cells because it can decrease the light reflectance over a large wavelength range. In this study, we have generated a textured structure on InAlP which is used for the window layer of the multi-junction III-V solar cells. Ultra-thin Pt layer (0.7 nm) has been used for wet etching mask. An array of nanosized pyramid shape formed on InAlP surface dramatically reduces the light reflectance up to 13.7% over a large wavelength range (i.e., $0.3{\sim}1.5{\mu}m$).