• Proceedings of the Korean Magnestics Society Conference
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• 2000.09a
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• pp.319-320
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• 2000

• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.271-274
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• 2010

We examined the tunneling current behaviors of magnetic tunneling junction (MTJ) cells utilizing conductive atomic force microscopy (AFM) interfaced with an external magnetic field generator. By introducing current through coils, a magnetic field was generated and then controlled by a current feedback circuit. This enabled the characterization of the tunneling current under various magnetic fields. The current-voltage (I-V) property was measured using a contact mode AFM with a metal coated conducting cantilever at a specific magnetic field intensity. The obtained magnetoresistance (MR) ratios of the MTJ cells were about 21% with no variation seen from the different sized MTJ cells; the value of resistance $\times$ area (RA) were 8.5 K-12.5 K $({\Omega}{\mu}m^2)$. Since scanning probe microscopy (SPM) performs an I-V behavior analysis of ultra small size without an extra electrode, we believe that this novel characterization method utilizing an SPM will give a great benefit in characterizing MTJ cells. This novel method gives us the possibility to measure the electrical properties of ultra small MTJ cells, namely below $0.1\;{\mu}m\;{\times}\;0.1\;{\mu}m$.

• Journal of Magnetics
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• v.14 no.1
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• pp.11-14
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• 2009

We investigated the I-V curves and differential tunneling conductance of two, CoFeB/MgO/CoFeB-based, magnetic tunnel junctions (MTJs): one with a low tunneling magnetoresistance (TMR; 22%) and the other with a high TMR (352%). This huge TMR difference was achieved by different MgO sputter conditions rather than by different annealing or deposition temperature. In addition to the TMR difference, the junction resistances were much higher in the low-TMR MTJ than in the high-TMR MTJ. The low-TMR MTJ showed a clear parabolic behavior in the dI/dV-V curve. This high resistance and parabolic behavior were well explained by the Simmons' simple barrier model. However, the tunneling properties of the high-TMR MTJ could not be explained by this model. The characteristic tunneling properties of the high-TMR MTJ were a relatively low junction resistance, a linear relation in the I-V curve, and conduction dips in the differential tunneling conductance. We explained these features by applying the coherent tunneling model.

• ETRI Journal
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• v.26 no.6
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• pp.669-672
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• 2004

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters $C_g=C_T=C_{clk}=1\;aF,\;R_T=5\;M{\Omega},\;V_{clk}=40\;mV$, and $V_{in}=20\;mV$. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.

• Journal of Magnetics
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• v.7 no.3
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.50-51
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• 2002

최근 실온에서 약 40％ 이상의 높은 자기저항(magnetoresistance, MR)을 나타내는 자기 터널 접합(magnetic tunnel junction, MTJ)이 보고되면서 비휘발성 자기메모리로의 응용을 눈앞에 두고 있다.[1]. 이에 본 실험에서는 Substrate / Ta (base electrode) / NiFe / PtMn (AF pinning layer) / CoFe (pinned) / Ru / CoFe (fixed) / Al-O/ CoFe (free) / NiFe (free) / Ta & Ru (Capping Layer)과 같은 MTJ 증착 구조를 사용하여, MTJ의 보다 향상된 특성을 확보하기 위한 노력으로서 Al-O 두께, 어닐링 조건(Field Intensity ＆ Sequence)변화 등을 시도하였다. (중략)

• Proceedings of the Korean Magnestics Society Conference
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• 2003.06a
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• pp.76-77
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• 2003

• Proceedings of the Korean Magnestics Society Conference
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• 2002.04a
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• pp.64-65
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• 2002

• Proceedings of the Korean Magnestics Society Conference
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• 2011.12a
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• pp.29-30
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• 2011

We have demonstrated the fabrication of sub 30 nm MTJ pillars with PMA characteristics. The multi-step IBE process performed at $45^{\circ}$ and $30^{\circ}$, using NER resulted in almost vertical side profiles. There deposition on the sidewalls of the NER prevented lateral etching of the resist hard mask allowing vertical MTJ side profile formation without any reduction in the lithographically defined resist lateral dimensions. For the 28nm STT-MTJ pillars, the measured TMR ratio was 13 % with resistance of 1 $k{\Omega}$, which was due to remaining redeposition layers less than 0.1 nm thick. With further optimization in multi-step IBE conditions, it will be possible to fabricate fully operating sub 30 nm perpendicular STT-MTJ structures for application to future non-volatile memories.