• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.1
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• pp.69-78
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• 2001

MPEG-4 visual conformance standard specifies methods to verify whether bitstreams and decoders meet the requirements at the specified profile and level. The test of decoders can be divided into two parts: the static test and the dynamic test. The static test can be performed by examining the decoder output with that of a reference decoder. This paper proposes design methods of test bitstreams for static test of texture decoding, and shows the test results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1046-1050
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• 2005

영상 정보의 발전으로 다양한 멀티미디어 서비스를 가능하게 하였고 네트워크와 IT의 발전으로 사용자가 풍부한 정보를 접할 수 있는 기회를 제공하였다. 이러한 동영상과 정지영상의 많은 정보를 압축하는 여러 방식 중에서 디지털 비디오 압축 관련 국제 표준안 중 MPEG-4와 H.264가 발표되었다. 유연성이 좋은 MPEG-4와 달리 H.264는 비디오 프레임의 효율적인 압축과 신뢰성을 강조 한다. 특히 H.264의 압축 기술은 HDTV처럼 큰 영상 뿐 아니라 카메라폰이나 DMB등의 특히 작은 크기의 영상에서 고품질의 영상을 보다 효율적으로 제공 한다. 본 논문은 기존의 동영상 압축 표준에 비하여 높은 압축성능과 유연성의 장점을 가지고 있고 표준 H.264/AVC에서 공간적 예측을 사용하여 비디오 프레임을 압축하는 방법인 Intra coding 에서 사용하는 여러 모드 중 4*4 예측모드를 연구하여 C언어를 이용한 최적화된 시뮬레이션과 Intra coding decoder의 성능평가를 통한 최적화를 실시하였고, 최적화된 예측 정보를 바탕으로 Intra coding decoder를 VHDL언어를 이용하여 하드웨어로 구현하였다.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.800-803
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• 2005

모바일 단말 기반 동영상 서비스 기술에 관한 연구는 최근에 이르기까지 활발히 수행되고 있으며, 인터넷 기반에서 상용화가 가능한 기술 분야를 모바일에 응용하는 시도가 계속되고 있다. 모바일 단말 기반 영상서비스와 관련하여 최신형 모바일 단말에서는 관련기술을 하드웨어적으로 구현하거나 독자적 동영상 압축기술을 적용한 소프트웨어적 구현을 통하여 동영상 서비스를 제공하고 있다. 그러나 상당한 비율을 점하고 있는 기존 모바일 단말에서는 이들 하드웨어 칩이 없거나 추가적으로 애드온(add-on) 할 수 있는 표준적인 방법이 정해지지 않아 최신의 동영상 서비스 기술을 제공받을 수 없다. 따라서 시시각각으로 변화하는 모바일 동영상 서비스 환경에 적극적으로 대처하기 위해서는 소프트웨어적 해결방안이 필수적이라는 인식이 대두되고 있다. 본 연구에서는 모바일 단말에서 소프트웨어 디코더를 이용하여 기존 단말에서 뿐만 아니라 향후 최신단말에서도 적극적으로 대처하기 위하여 H.264/AVC 기반 소프트웨어 디코더를 모바일 단말에 적용하는 방안에 대하여 제안한다.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.4
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• pp.309-318
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• 2004

This paper proposes the H.264-based selective fine granular scalable (FGS) coding scheme that selectively uses the temporal prediction data in the enhancement layer. The base layer of the proposed scheme is basically coded by the H.264 (MPEG-4 Part 10 AVC) visual coding scheme that is the state-of-art in codig efficiency. The enhancement layer is basically coded by the same bitplane-based algorithm of the MPEG-4 (Part 2) fine granular scalable coding scheme. In this paper, we introduce a new algorithm that uses the temproal prediction mechanism inside the enhancement layer and the effective selection mechanism to decide whether the temporally-predicted data would be sent to the decoder or not. Whenever applying the temporal prediction inside the enhancement layer, the temporal redundancies may be effectively reduced, however the drift problem would be severly occurred especially at the low bitrate transmission, due to the mismatch bewteen the encoder's and decoder's reference frame images. Proposed algorithm selectively uses the temporal-prediction data inside the enhancement layer only in case those data could siginificantly reduce the temporal redundancies, to minimize the drift error and thus to improve the overall coding efficiency. Simulation results, based on several test image sequences, show that the proposed scheme has 1∼3 dB higher coding efficiency than the H.264-based FGS coding scheme, even 3∼5 dB higher coding efficiency than the MPEG-4 FGS international standard.

• Journal of Broadcast Engineering
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• v.11 no.1 s.30
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• pp.116-129
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• 2006

The progress of data transmission technology through the Internet has spread a variety of realistic contents. One of such contents is multi-view video that is acquired from multiple camera sensors. In general, the multi-view video processing requires encoders and decoders as many as the number of cameras, and thus the processing complexity results in difficulties of practical implementation. To solve for this problem, this paper considers a simple multi-view system utilizing a single encoder and a single decoder. In the encoder side, input multi-view YUV sequences are combined on GOP units by a video mixer. Then, the mixed sequence is compressed by a single H.264/AVC encoder. The decoding is composed of a single decoder and a scheduler controling the decoding process. The goal of the scheduler is to assign approximately identical number of decoded frames to each view sequence by estimating the decoder utilization of a Gap and subsequently applying frame skip algorithms. Furthermore, in the frame skip, efficient frame selection algorithms are studied for H.264/AVC baseline and main profiles based upon a cost function that is related to perceived video quality. Our proposed method has been performed on various multi-view test sequences adopted by MPEG 3DAV. Experimental results show that approximately identical decoder utilization is achieved for each view sequence so that each view sequence is fairly displayed. As well, the performance of the proposed method is examined in terms of bit-rate and PSNR using a rate-distortion curve.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.