• The Journal of Korean Association of Computer Education
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• v.16 no.3
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• pp.99-105
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• 2013

The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.91-98
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• 2008

Domestic standard for Korean T-DMB includes MPEG-4 BSAC (Bit Sliced Arithmetic Coding) audio coding that has been established in 2003. This paper presents an implementation and optimization of MPEG-4 BSAC Audio Decoder on ARM926EJ-S processor. Tools and modules of the BSAC audio decoder were implemented with 32-bit fixed point operations. Further optimization was accomplished using ARM926EJ-S Inline Assembly. The optimization was based on the total number of multiplications and MAC (Multiply and Accumulation) operations causing most of core cycles of ARM926EJ-S, and also based on analysis of ARMv5 instructions. The result of optimization was evaluated on the basis of MIPS (Million Instruction per second). Implementation results show that BSAC bitstream at 96kbps can be decoded in real-time at 65MHz CPU clocks.

• Journal of Internet Computing and Services
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• v.4 no.6
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• pp.13-24
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• 2003

Grid technology requires use of geographically distributed resources from multiple domains. Resource monitoring services or tools consisting sensors or agents will run on many systems to find static resource information (such as architecture vendor, OS name and version, MIPS rate, memory size, CPU capacity, disk size, and NIC information) and dynamic resource information (CPU usage, network usage(bandwidth, latency), memory usage, etc.). Thus monitoring itself may cause system overhead. This paper proposes the optimal monitoring interval to reduce the cost of monitoring services and the dynamic monitoring interval to measure monitoring events accurately. By employing two features, we find out unnecessary system overhead is significantly reduced and accuracy of events is still acquired.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.825-827
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• 1997

This paper presents a robot which is steered by vision system. The proposed robot system has an AM188ES CPU(5.3 MIPS) and 2DC motors with encoder and turns accurately at any speed and shows a movement like a human controlled car using a steering wheel. To the robot only steering angle value is sent without considering the speed. We present how to control this robot using our real time vision system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.1
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• pp.97-107
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• 2002

In this paper, we propose the realization of on-line handwritten Chinese character recognition for mobile personal digital assistants (PDA). We focus on the development of an algorithm having a high recognition performance under the restriction that PDA requires small memory storage and less computational complexity in comparison with PC. Therefore, we use index matching method having computational advantage for fast recognition and we suggest a unit reconstruction method to minimize the memory size to store the character models and to accomodate the various changes in stroke order and stroke number of each person in handwriting Chinese characters. We set up standard model consisting of 1800 characters using a set of pre-defined units. Input data are measured by similarity among candidate characters selected on the basis of stroke numbers and region features after preprocessing and feature extracting. We consider 1800 Chinese characters adopted in the middle and high school in Korea. We take character sets of five person, written in printed style, irrespective of stroke ordering and stroke numbers. As experimental results, we obtained an average recognition time of 0.16 second per character and the successful recognition rate of 94.3% with MIPS R4000 CPU in PDA.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.251-254
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• 2003

본 논문의 목표는 디지털방송과 인터넷의 융합에 따른 MPEG-2/4/7 방송 및 인터넷 콘텐츠을 비롯한 게임등과 같은 다양한 멀티미디어 서비스를 제공하기 위한 차세대 지능형 고품질 홈 엔터테인먼트 시스템 Platform 개발이다. 디지털 방송과 데이터방송 수신이 가능한 Set-Top Box기능, 수신된 방송의 저장 및 재생이 가능한 PDR 기능, MPEG-2 형식을 MPEG-4 형식으로 변환하는 Transcoding 기능, VOD 서비스를 제공하기 위한 Streaming 기능 등을 지원할 수 있는 시스템의 구조를 설계하였다. 이러한 지능형 고품질 서비스를 지원하기 일해 고성능 시스템이 필요하다. 시스템 제어를 위한 CPU 로는 PMC-Sierra사의 MIPS Architecture에 기반을 둔 RM5231 을 채택하고, MPEC-4 Decoding, BIFS Presentation Engine과 Streaming 서비스와 MPEC-7 Metadata Generator/Parser 을 위해 ARM Architecture에 기반을 둔 Intel80200 Processor 를 채택하였다. 또한, 디지털방송을 위한 MPEC-2 Decoder Chip 인 Teraloglc 사의 TL811 System Controller 와 TL851 Graphics& Display Processor 를 채택하였다. 개발된 시스템을 테스트하기 위하여 DVB-MHP Server와 MPEG-4 IP Streaming Server 를 구축하여 디지털 방송과 Streaming 서비스를 테스트하였다.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.165-167
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• 2006

In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 KHz (0.3 MIPS) while consuming only about few pJ/instruction.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.284-287
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• 2004

본 논문의 목표는 일체형 디지털 TV에서 디지털 방송 수신과 방송 컨텐츠를 녹화, 저장, 재생이 가능할 뿐만 아니라 조만간 시작될 데이터 방송을 수신할 수 있는 내장형 디지털 방송수신 및 개인 비디오 저장 시스템 Platform 개발이다. 디지털 방송과 데이터방송 수신이 가능한 Set-Top Box 기능, 수신된 방송의 저장 및 재생이 가능한 PVR 기능을 지원할 수 있는 시스템의 구조를 설계하였다. 고품질 디지털 방송 서비스가 본격적으로 시작됨에 따라 디지털 방송 수신기와 PVR 기능이 복합된 제품의 수요가 증가할 것으로 예상되며 이러한 고성능 복합시스템은 필수적일 것이다. 이러한 기능을 수행하기 위하여 시스템 제어를 위한 CPU로는 PMC-Sierra 사의 MIPS Architecture에 기반을 둔 RM5231을 채택하고, Teralogic 사의 TL811 System Controller을 채택하여 시스템을 이루고 있는 각종 디바이스를 구성하고, MPEG-2 Demux/Decoding을 위해 Teralogic TL851 Graphics & Display Processor을 채택하였다. 개발된 시스템을 테스트하기 위하여 현재 각 방송사들의 시험 방송을 수신하고 PVR 기능을 테스트하였다.