• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.105-113
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• 1994

This paper introduces the Parallel Advanced Loosely coupled Multiprocessor (PALM) architecture, which is based on HCH(m,p), where m is number of links per a communication processor (CP) and p is the number of application processors (APs) connected to the CP. communication links between a pair of CPs and/or between a CP and an AP, are made of dual-Port RAMs, which provide fast and reliable word-parallel communication between processors. Among the wide spectrum of HCH networks, HCH(m,2) is also known to be a cost optimal topology, such that HCH(m,2) consists of the largest number of APs retaining the minimal number of CPs and communication links. We also implement a testbed based on HCH(2,2). The experiment result shows that the small communication/computation ratio of the PALM system would realize fine-grain parallelism on message-passing MIMD systems.

• Journal of KIISE:Databases
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• v.29 no.1
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• pp.44-57
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• 2002

Multiple spatial queries are defined as two or more spatial range queries to be executed at the same time. The primary processing of internet-based map services is to simultaneously execute multiple spatial queries. To improve the throughput of multiple queries, the time of disk I/O in processing spatial queries significantly should be reduced. The declustering scheme of a spatial dataset of the MIMD architecture cannot decrease the disk I/O time because of random seeks for processing multiple queries. This thesis presents query scheduling strategies to ease the problem of inter-query random seeks. Query scheduling is achieved by dynamically re-ordering the priority of the queued spatial queries. The re-ordering of multiple queries is based on the inter-query spatial relationship and the latency of query processing. The performance test shows that the time of multiple query processing with query scheduling can be significantly reduced by easing inter-query random seeks as a consequence of enhanced hit ratio of disk cache.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.