• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.621-622
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• 2017

In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.

• Journal of Korea Trade
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• v.24 no.8
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• pp.81-100
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• 2020

Purpose - Based on complexity theory, this study develops a configurational model to predict the profitability of Halal cosmetics firms in the Indonesian and Malaysian markets. The proposed research model involves two level configurations-industry context and selling strategies-to predict high and low scores of a firm's profitability. The industry context configuration model comprises industry stability, product homogeneity, price sensitivity, and switching cost. Selling strategies include customer-focused, competitor-focused, and margin-focused approaches. Design/methodology - This is the first empirical study that calculates causal models using a combination of industry context and selling strategy factors to predict profitability. Data obtained from the marketing managers of cosmetics firms are used to test the proposed configurational model using fuzzy-set qualitative comparative analysis (fsQCA). It contributes to the current knowledge of business marketing by identifying the factors necessary to achieve profitability using analysis of condition (ANC). Findings - The results revealed that unique and distinct models explain the conditions for high and low profitability in the Indonesian and Malaysian halal cosmetic markets. While customer-focused selling strategy is necessary to attain a higher profit in both the markets, margin-focused selling strategy appears to be an essential factor only in Malaysia. Complexity of the interactions of selling strategies with industry factors and differences between across two study markets confirmed that complexity theory can support the research configurational model. The theoretical and practical implications are also illustrated. Originality/value - Despite the rapid growth of the global halal industry, there is little knowledge about the halal cosmetic market. This study contributes to the current literature of the halal market by performing a set of asymmetric analytical approaches using a complex theoretical model. It also deepens our understating of how the Korean firms can approach the Muslim consumer's needs to generate more beneficial turnover/revenue.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...

• Journal of IKEEE
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• v.23 no.1
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• pp.207-213
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• 2019

In this paper, we propose a low-complexity feature detection algorithm for object tracking and present hardware architecture design and implementation results for real-time processing. The existing Shi-Tomasi algorithm shows good performance in object tracking applications, but has a high computational complexity. Therefore, we propose an efficient feature detection algorithm, which can reduce the operational complexity with the similar performance to Shi-Tomasi algorithm, and present its real-time implementation results. The proposed feature detector was implemented with 1,307 logic slices, 5 DSP 48s and 86.91Kbits memory with FPGA. In addition, it can support the real-time processing of 54fps at an operating frequency of 114MHz for $1920{\times}1080FHD$ images.

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.65-71
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• 2012

An OS-CFAR (Ordered Statistics CFAR) based on a sorting algorithm is useful for automotive radar systems in a multi-target situation. However, while the typical cell-averaging CFAR has low computational complexity, the OS-CFAR has much higher computation effort. In this paper, we design the new OS-CFAR architecture with a low computational effort. In the proposed method, since one time sorting processing is performed for the decision of the CFAR threshold, the whole processing effort can be reduced. When the fast sorting technique is employed, the computing time of the proposed OS-CFAR is always much shorter compared with typical OS-CFAR method regardless of the data size. We also present the processing result of proposed architecture using the real radar data.

• Journal of Ubiquitous Convergence Technology
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• v.2 no.2
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• pp.67-77
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• 2008

Representation of various types of information in an interactive virtual reality environment on mobile devices had been an attractive and valuable research in this new era. Our main focus is presenting spatial indoor location sensing information in 3D perception in mind to replace the traditional 2D floor map using handheld PDA. Designation of 3D virtual reality by Virtual Reality Modeling Language (VRML) demonstrates its powerful ability in providing lots of useful positioning information for PDA user in real-time situation. Furthermore, by interpolating portal culling algorithm would reduce the 3D graphics rendering time on low power processing PDA significantly. By fully utilizing the CC2420 chipbased sensor nodes, wireless sensor network was established to locate user position based on Received Signal Strength Indication (RSSI) signals. Implementation of RSSI-based indoor tracking method is low-cost solution. However, due to signal diffraction, shadowing and multipath fading, high accuracy of sensing information is unable to obtain even though with sophisticated indoor estimation methods. Therefore, low complexity and flexible accuracy refinement algorithm was proposed to obtain high precision indoor sensing information. User indoor position is updated synchronously in virtual reality to real physical world. Moreover, assignment of magnetic compass could provide dynamic orientation information of user current viewpoint in real-time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.48-55
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• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• Journal of KSNVE
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• v.1 no.1
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• pp.29-38
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• 1991

The performance of silencer system is controlled by the geometrical parameters such as the relative location of inlet and outlet ports, size of main chamber, and cross sectional geometry of inlet-outlet ports and main chamber of silencer. In addition to these parameters, the presence of mean flow and temperature gradient along the silencer also affects the acoustic characteristics of silencer system. Due to the complexity of silencer, it is not straight forward to design the appropriate silencer system. In this paper, a design methodology based on an oustic analysis of silencer system is proposed ; low frequency and high frequency tuning method.