• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.250-255
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• 2006

A low cost PDP sustain power supply is proposed based on flyback topology using Boundary Conduction Mode(BCM) to control input current regulation. This method guarantees DCM condition to regulate the input current harmonics under all load conditions. An excessive voltage stress due to the link voltage increase can be suppressed by removing link capacitor and adjusting transformer turns ratios, which makes it possible to be used for universal line applications. The proposed converter is tested with a 400W(200V-2A output) prototype circuit.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.155-162
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• 1999

A bare chip packaging technology by an encapsulated flip chip bonding on a build-up printed circuit board has emerged in 1991. Since then, it enabled a high density and low cost semiconductor packaging such as a direct chip bonding on mother board and high density surface mount components, such as BGA and CSP. This technology can respond to various requirements from applications and is considered to take over a main role of semiconductor packaging in the next decade.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 춘계학술대회
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• pp.21-40
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• 2006

[ ${\Box}$ ] Opportunities for PRAM Nearly ideal memory characteristics Potential for high density & low cost memory ${\Box}$ Technical Challenges Writing current reduction is the most urgent issue. ${\to}$ chalcogenide, programming volume, current density, heat loss control Improvement of writing speed, reliability ${\Box}$ Prospects (PRAM as a Mainstream Memory) Evenn, We have demonstrated 256Mb PRAM Realization of high density and low cost PRAM with good reliability will be key succss factor. We need to develop PRAM specific applications.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.641-643
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• 2006

Add-Vision has developed a low-cost print technology for P-OLED displays on flexible substrates that meets several essentials for a new technology including: (1) Functionality including low DC voltage and wide color gamut; (2) Utilization of inexpensive tools; (3) Performance matching entry applications and markets. AVI's process is based on large-area printing of a combination of doped emissive and air-stable cathode inks utilizing truly low-cost tools to create printed P-OLEDs.

• Journal of Electrochemical Science and Technology
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• 제15권1호
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• pp.1-13
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• 2024

This paper presents applications of lithium-sulfur (Li-S) energy storage batteries, while showing merits and demerits of several techniques to mitigate their electrochemical challenges. Unmanned aerial vehicles, electric cars, and grid-scale energy storage systems represent main applications of Li-S batteries due to their low cost, high specific capacity, and light weight. However, polysulfide shuttle effects, low conductivities, and low coulombic efficiencies signify key challenges of Li-S batteries, causing high volumetric changes, dendritic growths, and limited cycling performances. Solid-state electrolytes, interfacial interlayers, and electrocatalysts denote promising methods to mitigate such challenges. Moreover, nanomaterials have capability to improve kinetic reactions of Li-S batteries based on several properties of nanoparticles to immobilize sulfur in cathodes, stabilizing lithium in anodes while controlling volumetric growths. Li-S energy storage technologies are able to satisfy requirements of future markets for advanced rechargeable batteries with high-power densities and low costs, considering environmentally friendly systems based on renewable energy sources.

• 디지털산업정보학회논문지
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• 제8권2호
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• pp.177-188
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• 2012

GIS provides the various analyzing and displaying using diverse spatial data have supported the powerful functionality and friendly user-interface. But, early GIS software is developed as package tool, it have many difficulties with reducing the cost of developing GPS application and satisfying the various user requirements. At present, the developed GPS applications across multiple domains, despite the common features are built separately for each domain in terms of software engineering development followed out waste of time and money expenditure. However, common features between GPS applications, if deployed as a component assembly and reuse components in terms of enabling the two kinds of component-based development can bring out the beneficial results. In this paper, we described the Analysis and design of GPS ApplicationsS based on Component. Each GPS component is composed of many objects accomplish the atomic service processing and cooperate with each other. And, GPS components meets the qualifications of thc low cost of developing GPS application because of the reusability and re-composition.

• 신재생에너지
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• 제1권1호
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• pp.37-43
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• 2005

High-efficiency silicon solar cells have potential applications on mobile electronics and electrical vehicles. The fabrication processes of the high efficiency cells necessitate com placated fabrication precesses and expensive materials. Ti/Pd/Ag metal contact has been used only for limited area In spite of good stability and low contact resistance because of Its expensive material cost and precesses. Screen printed contact formed by Ag paste causes a low fill factor and a high shading loss of commercial solar cells because of high contact resistance and a low aspect ratio. Low cost Ni/Cu metal contact has been formed by using a low cost electroless and electroplating. Nickel silicide formation at the interface enhances stability and reduces the contact resistance resulting In an energy conversion efficiency of $20.2\%\;on\;0.50{\Omega}cm$ FZ wafer. Tapered contact structure has been applied to large area solar cells with $6.7\times6.7cm^2$ in order to reduce power losses by the front contact The tapered front metal contact Is easily formed by the electroplating technique producing $45cm^2$ solar cells with an efficiency of $21.4\%$ on $21.4\%\;on\;2{\Omega}cm$ FZ wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.168-169
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• 2007

Organic transistors are promising in the future development of active devices for flexible, low-cost and large-area photoelectric devices. However, conventional organic field-effect transistors have lowspeed, low-power, and relatively high operational voltage. Vertical type transistors show high-speed and high-current characteristics and are suitable for driver elements of flexible displays.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.27-27
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• 2000