• 전력전자학회논문지
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• 제26권2호
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• pp.96-105
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• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

• Journal of Power Electronics
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• 제19권2호
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• pp.529-539
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• 2019

The modular multilevel converter (MMC) has become a promising topology for high-voltage direct current (HVDC) transmission systems. To control a MMC system properly, the ac-side current, circulating current and submodule (SM) capacitor voltage are taken into consideration. This paper proposes a low-computation indirect model predictive control (IMPC) strategy that takes advantages of the conventional MPC and has no weighting factors. The cost function and duty cycle are introduced to minimize the tracking error of the ac-side current and to eliminate the circulating current. An optimized merge sort (OMS) algorithm is applied to keep the SM capacitor voltages balanced. The proposed IMPC strategy effectively reduces the controller complexity and computational burden. In this paper, a discrete-time mathematical model of a MMC system is developed and the duty ratio of switching state is designed. In addition, a simulation of an eleven-level MMC system based on MATLAB/Simulink and a five-level experimental setup are built to evaluate the feasibility and performance of the proposed low-computation IMPC strategy.

• 융합신호처리학회논문지
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• 제12권3호
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• pp.204-211
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• 2011

주변의 환경을 감시하기 위한 요즘의 임베디드 시스템은 고성능의 실시간 데이터 처리능력 및 넓은 통신 대역폭을 요구할 뿐만 아니라 신호처리를 위한 임베디드 시스템의 적은 소비전력소모를 요구하고 있다. 하지만 휴대용의 성격이 있는 임베디드 시스템에 사용되는 배터리의 용량은 이러한 요구조건을 장기간 만족시킬 수 있을 만큼의 기술로는 아직 발전하지 못하였다. 본 논문에서는 이러한 상황을 극복하기 위해 저에너지로 동작하면서도 사건을 정확하게 탐지하기 위한 새로운 접근법을 제안한다. 설계된 방식은 시스템 주변에서 발생하는 사건을 탐지하기 위해 여러 알고리즘이 계층적으로 연결되어 있는 구조를 가지고 있다. 이러한 계층적 사건 탐지기를 구성하는 다양한 사건 탐지 알고리즘들의 정확도에 대한 확률적 특성 변화 따른 에너지 소모의 특성 변화를 보여주고 이들의 관계를 실험을 통하여 분석적으로 설명한다 뿐만 아니라 사건의 정적, 동적 특성에 따라 높은 사건 탐지 정확도를 유지하면서 저에너지로 동작하기 위한 다른 방식들을 기술한다.

• 한국전자통신학회논문지
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• 제13권5호
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• pp.1037-1042
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• 2018

최근 인간의 뇌를 모방하여 정보를 학습하고 처리하는 뉴로모픽 기술에 대한 연구는 꾸준히 진행되고 있다. 뉴로모픽 시스템의 하드웨어 구현은 다수의 간단한 연산절차와 고도의 병렬처리 구조로 구성이 가능하여, 처리속도, 전력소비, 저 복잡도 구현 측면에서 상당한 이점을 가진다. 또한 저 전력, 소형 임베디드 시스템에 적용 가능한 뉴로모픽 기술에 대한 연구가 급증하고 있으며, 정확도 손실 없이 저 복잡도 구현을 위해서는 입력데이터의 차원축소 기술이 필수적이다. 본 논문은 멀티모달 센서 데이터를 처리하기 위해 멀티모달 센서 시스템, 다수의 뉴론 엔진, 뉴론 엔진 컨트롤러 등으로 구성된 경량 인공지능 엔진과 특징추출기를 설계 하였으며, 이를 위한 병렬 뉴론 엔진 구조를 제안하였다. 설계한 인공지능 엔진, 특징 추출기, Micro Controller Unit(MCU)를 연동하여 제안한 경량 인공지능 엔진의 성능 검증을 진행하였다.

• 한국산업정보학회논문지
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• 제19권4호
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• pp.25-32
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• 2014

전력선통신은 스마트그리드 기반의 서비스가 제공될 수 있는 네트워크를 위한 미래지향적 기술이다. 전력선통신 채널의 주파수 선택적 페이딩이 있는 환경에서, 직교주파수분할다중화 기술은 신뢰성 있는 통신을 제공한다. 본 논문에서는 직교주파수분할다중화 기반의 전력선통신 시스템에서 은닉학습신호를 이용한 주파수사용효율이 높은 기법을 제안한다. 은닉학습신호를 사용하면 채널 추정용 주파수를 따로 소모하지 않고도 채널 추정이 가능하고, 이는 데이터와의 간섭을 줄일 수 있는 학습신호에 할당된 파워를 이용해서 해결할 수 있다. 컴퓨터 시뮬레이션을 통해 제안한 기법이 기존의 기법들에 비해 저전압 및 중전압 송전 라인에서 높은 성취 가능한 데이터 율을 보여준다.

• 전기학회논문지P
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• 제59권1호
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• pp.100-105
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• 2010

This paper describes a capacity of distributed generation which will be interconnected at low voltage distribution systems. In order to set the capacity of distributed generation, a voltage variation of distribution system is considered. Besides, the capacity of distributed generation is classified according to a capacity of pole transformer and loads. The system constructions in this paper are analyzed by using PSCAD/EMTDC. In the immediate future, it is expected to increase the installation of New and renewable energy systems which are generally interconnected to distribution power systems in the form of distributed generations like photovoltaic system, wind power and fuel cell. So the study of this kind would be needed to limit the capacity of distributed generation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1999년도 제14차 학술회의논문집
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• pp.9-12
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• 1999

This paper presents the development of a control architecture for the autonomous underwater vehicle (AUV) with VARIVEC (variable vector) propeller. Moreover this paper also describes the new technique of controlling the servomotors using the Field Programmable Gate Array (FPGA). The AUVs are being currently used fur various work assignments. For the daily measuring task, conventional AUV are too large and too heavy. A small AUV will be necessary for efficient exploration and investigation of a wide range of a sea. AUVs are in the phase of research and development at present and there are still many problems to be solved such as power resources and underwater data transmission. Further, another important task is to make them smaller and lighter for excellent maneuverability and low power. Our goal is to develop a compact and light AUV having the intelligent capabilities. We employed the VARIVEC propeller system utilizing the radio control helicopter elements, which are swash plate and DC servomotors. The VARIVEC propeller can generate six components including thrust, lateral force and moment by changing periodically the blade angle of the propeller during one revolution. It is possible to reduce the number of propellers, mechanism and hence power sources. Our control tests were carried out in an anechoic tank which suppress the reflecting effects of the wall surface. We tested the developed AUV with required performance. Experimental results indicate the effectiveness of our approach. Control of VARIVEC propeller was realized without any difficulty.

• 전력전자학회논문지
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• 제19권1호
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• pp.57-63
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• 2014

In this paper a bidirectional DC-DC converter is proposed for renewable energy systems, eco-friendly vehicles, energy storage systems, uninterruptible power supply(UPS) systems and battery test equipments. The two-stage bidirectional converter employing a fixed-frequency series loaded resonant converter is designed to be capable of operating under zero-current-switching turn on and turn off regardless of voltage and load variation, and hence its magnetic components and EMI filters can be optimized. And efficiencies and volumes of the two-stage bidirectional converters are compared according to configuration of isolated and non-isolated parts and a two-stage topology suitable for low voltage and high current applications is proposed. A 12kW(12V, 1000A) prototype of the proposed converter has been built and tested to verify the validity of the proposed operation.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Journal of Information Processing Systems
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• 제15권6호
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.