• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.21-27
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• 2013

In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.24-31
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• 2010

A receiver architecture with low complexity for chirp spread spectrum (CSS) of IEEE 802.15.4a is proposed. To demodulate the received signal at the highest signal to noise power ratio, matched filter is generally adopted for the receiver of wireless communication systems. It is, however, not resonable to adjust the matched filter to the receiver of CSS whose objectives are low complexity, low cost and low power consumption since complexity of the matched filter is high. In this paper, we propose a new receiver architecture using differential multiplication and accumulator not matched filter for demodulation. Also, bi-orthogonal decoder implemented by only adder/subtractor is proposed. The hardware resources for implementation are reduced in the proposed receiver architecture, although bit error rate performance is low compared with the receiver architecture based on the matched filter.

• ETRI Journal
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• v.39 no.4
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1839-1844
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• 2015

The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

• Journal of The Korean Society of Integrative Medicine
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• v.9 no.4
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• pp.167-181
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• 2021

Purpose : This study was conducted to investigate whether phonetic complexity affected the type and frequency of articulation errors and the acoustic duration of consonants and words produced by children with functional articulation and phonological disorders. Methods : The participants in this study were 20 children with functional articulation and phonological disorders and 20 children without such disorders who were between 3 years 7 months old and 4 years 11 months old. The participants were asked to name what they saw in pictures and their responses were recorded. The types and frequencies of articulation errors and the acoustic duration of words were analyzed and words were categorized as being of either 'high' or 'low' phonetic complexity. The acoustic duration of initial and final consonants and vowels following initial consonants were compared between the groups according to articulatory complexity. Results : Children with functional articulation and phonological disorders produced articulation errors more frequently when saying high complexity words and had longer word duration when saying low-complexity words than children without such disorders. There was no major difference in initial and final consonant duration between the groups. but the main effect of articulatory complexity on the duration of both consonants was significant. Conclusion : These results suggest that the articulatory-phonic structure of words influences the speech motor control ability of children with functional articulation and phonological disorders. When articulating consonants, children with functional articulation and phonological disorders had speech motor control ability similar to that of children without such disorders.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.3
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• pp.19-30
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• 2007

In this paper, we propose low-complexity implementation of orthogonal frequency division multiple access (OFDMA) timing delay detector with multiple receive antennas for broadband wireless access (BWA). First, in order to reduce the computational complexity, the detection structure which rotates the phase of the received ranging symbols is introduced. Second, we propose the detection structure with the N-point/M-interval fast Fourier transform structure and a frequency-domain average-power estimator for complexity reduction without sacrificing the system performance. Finally, simulation results for the proposed structures and complexity comparison of the existing structure with the proposed detectors are presented.

• ETRI Journal
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• v.26 no.2
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• pp.122-135
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• 2004

Although frame-based MPEG-4 video services have been successfully deployed since 2000, MPEG-4 video coding is now facing great competition in becoming a dominant player in the market. Object-based coding is one of the key functionalities of MPEG-4 video coding. Real-time object-based video encoding is also important for multimedia broadcasting for the near future. Object-based video services using MPEG-4 have not yet made a successful debut due to several reasons. One of the critical problems is the coding complexity of object-based video coding over frame-based video coding. Since a video object is described with an arbitrary shape, the bitstream contains not only motion and texture data but also shape data. This has introduced additional complexity to the decoder side as well as to the encoder side. In this paper, we have analyzed the current MPEG-4 video encoding tools and proposed efficient coding technologies that reduce the complexity of the encoder. Using the proposed coding schemes, we have obtained a 56 percent reduction in shape-coding complexity over the MPEG-4 video reference software (Microsoft version, 2000 edition).

• Journal of Positioning, Navigation, and Timing
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• v.11 no.2
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• pp.91-98
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• 2022

In the next generation wireless communication system, the beamforming technique based on a massive antenna is one of core technologies for transmitting and receiving huge amounts of data, efficiently and accurately. For highly performed and highly reliable beamforming, it is required to accurately estimate the Angle of Arrival (AOA) for the desired signal incident to an antenna. Employing the massive antenna with a large number of elements, although the accuracy of the AOA estimation is enhanced, its computational complexity is dramatically increased so much that real-time communication is difficult. In order to improve this problem, AOA estimation algorithms based on the massive antenna with the low computational complexity have been actively studied. In this paper, we compute and analyze the computational complexity of the cascade AOA estimation algorithm based on the Flexible Massive Concentric Circular Array (FMCCA). In addition, its computational complexity is compared to conventional AOA estimation techniques such as the Multiple Signal Classification (MUSIC) algorithm with the high resolution and the Only Beamspace MUSIC (OBM) algorithm.

• Journal of Broadcast Engineering
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• v.18 no.6
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• pp.808-815
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• 2013

In this paper, we propose a novel fast and low-complexity Motion Estimation (ME) algorithm for Ultra High Definition (UHD) High Efficiency Video Coding (HEVC). Motion estimation occupies 77~81% of the amount of computation in HEVC. After all, the main key of video codec implementation is to find a fast and low-complexity motion estimation algorithm and architecture. We analyze the previous motion estimation algorithms and propose three optimal algorithm to reduce the computation proportion for HEVC. The proposed algorithm uses only 0.36% of the amount of operations compared to full search algorithm while maintaining compression performance with slight loss of 1.1%.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.447-448
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• 2008

This paper presents a low-complexity design and implementation results of a multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) symbol detector for high speed wireless LAN (WLAN) systems. The proposed spatial division multiplexing (SDM) symbol detector is designed by HDL and synthesized to gate-level circuits using 0.18um CMOS library. The total gate count for the symbol detector is 238K.