• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.90-92
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• 2002

This paper presents an improved C-Dump converter system for switched reluctance motors(SRM). The proposed C-Dump converter derived from the conventional converter for SRM. The proposed converter could overcome the limitation of the conventional C-Dump converter, and could reduce the whole cost of the SRM system since the voltage stress of the dump switch $T_d$ is reduced to $V_{dc}$ when compared with $2V_{dc}$ for the conventional C-Dump converter. The attractive features of the proposed converters are; high-efficient and low-cost, elimination of dump inductor, simple control strategy, smaller size arid light weight. The proposed converter is able to be fast magnetization by $2V_{dc}$, which is sum of the input voltage and charging voltage of the dump capacitor. Also, this topology has many advantages such as freewheeling of phase winding without complex control, reduction of current ripple, reduction of torque ripple, and reduction of switching frequency. Simulation demonstrates the good performance of the converter.

• Journal of Power Electronics
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• v.13 no.2
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• pp.232-242
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• 2013

To obtain phase currents information in AC drives, shunt sensing technology is known to show great performance in cost-effectiveness and therefore it is widely used in low cost applications. However, shunt sensing methods are unable to acquire phase currents in certain operation conditions. This paper deals with the derivation of the boundary conditions for phase current reconstruction in three-shunt sensing inverters and proposes a voltage injection method to expand the measurable areas. As the boundary conditions are deeply dependent on the switching patterns, they are typically analyzed on the voltage vector plane for space vector pulse width modulation (SVPWM) and discontinuous pulse width modulation (DPWM). In the proposed method, the voltage injection and its compensation are conducted within one sampling period. This guarantees fast current reconstruction and the injected voltage is decided so as to minimize the current ripple. In addition to the voltage injection method, a sampling point shifting method is also introduced to improve the boundary conditions. Simulation and experimental results are presented to verify the boundary condition derivation and the effectiveness of the proposed voltage injection method.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.7
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• pp.675-682
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• 2009

Instead of direct driving like BLDC, the induction principle is adopted as a driving one for planar stage. The stage composed of four linear induction motors put in square type is activated by two-axial forces; low-frequency attractive force and thrust force of the linear induction motors. Here, the modified vector control whose new inputs are q-axis current and dc current biased to three phase current instead of d-axis current or flux current is applied extensively to overall motion of the stage. For the developed system, the precision step test and the constant velocity test are tried to guarantee its feasibility for TFT-LCD pattern inspection. However, to exclude a discontinuity due to phase shift and minimize a force ripple synchronized with the command frequency, the initial system is revised to the antagonistic structure over the full degree of freedom. Concretely describing, the porous air bearings guide an air-gapping of the stage up and down and a pair of liner induction motors instead of single motor are activated in the opposite direction each other. The performances of the above systems are compared from trapezoid tracking test and sinusoidal test.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.181-184
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• 2005

Operating conditions of photovoltaic power generator is very sensitive to the PV modules. The PV module's control is an importance issue in the removing DC ripple noise. In this paper, the phase-shifted-carrier technique, which is a new three-step dc-dc power multi-converter schemes, is applied to solar generator system to improve the output current waveform. The novel type of three-step dc-dc converter presented has many features such as the good output waveform, high efficiency, low switching losses, low acoustic noise. The circuit configuration is constructed by the conventional full-bridge type converter circuit using the isolated DC power supply for which the solar cell is very suitable. In the end, a circuit design for understanding three-step dc-dc converter and new solar power system were presented

• Journal of Power Electronics
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• v.16 no.2
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• pp.447-454
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• 2016

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.2
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• pp.55-60
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• 2006

In order to suppress lasing oscillation and obtain high light power, We have proposed a novel SLD which is formed with a straight and tilted waveguide. The window region is used to suppress lasing oscillation and reduce the facet reflectivity. High power and low reflectivity is obtained by the straight and tilted waveguide. Based on the theoretical analysis, we have fabricated the SLD with the waveguide of 500 $\mu$m length and window region of 50 $\mu$m by LPE equipment. Through the measurements of optical characteristics, the output light power of 3 mW was obtained at the 150 mA CW injection current and 25$^{circ}C$. We have confirmed that the proposed SLD has a 0.8 dB spectrum ripple lower than 1 dB which is sufficiently low reflectivity for preventing lasing.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.603-609
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• 2008

Slotless linear brushless DC motor are widely used in precision machine applications because of their advantages such as low of detent force, negligible iron loss. But they have a disadvantage such as low thrust density, thrust ripple, and excessive use of permanent magnet materials. These lead to undesirable performance and high production cost. In this paper, we deal with the design and characteristics investigation of a air-core tubular linear brushless DC(TLBLDC) motor with air-core stator and permanent magnet mover. And to investigate the static and dynamic characteristics of air-core TLBLDC motor, the prototype machine is manufactured and analyzed by F.E.M. and Matlab simulink simulations. Especially, dynamic characteristics of air-core TLBLDC motor driven with 6 step inverter are simulated by F.E.M.coupling with external circuit and Matlab simulink program, and measured for the prototype motor. The simulation results are compared to the experimental results such as current waves, thrust and speed curve.

• 한국석유지질학회:학술대회논문집
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• spring
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• pp.29-37
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• 1998

The sedimentary succession on the northern coast of Jindo and the adjacent area comprises the thinly bedded, fine-grained deposits of an epiclastic sandstone, siltstone, black shale/mudstone, and cherty mudstone (ca. 200m in vertical thickness), which are interpreted as the finely stratified turbidites mainly by density underflow-induced currents. Most deposits can be divided into eight facies: thin-bedded, ash-rich massive sandstone layer (mS), graded and laminated mudstone layer (glM), graded mudstone layer with ripple lamination (rM), laminated and graded siltstone layer (lgZ), finely laminated black shale layer (IBS), structureless mudstone layer (mM), thin-bedded cherty mudstone layer (lCM), and contorted and laminated mudstone layer (dlM), The thin-bedded, ash-rich sandstone facies is interpreted to be deposited from high-density turbid underflows during a relatively large flooding. Most thinly bedded mudstone facies would be deposited from low-density turbid underflows (turbidity currents) with some different hydrodynamic condition and sediment concentration during the high discharge of river water. Whereas the structureless mudstone facies may result from raining down of suspended sediment intermittently supplied by overflows and interflows. From the entire succession, graded and laminated mudstone layers interbedded with thin-bedded, ash-rich massive sandstone are dominant in the lower part of the succession, and graded mudstone layers with ripple lamination ripple lamination occur mainly in the middle part of it. On the other hand, iaminated/raded siltstone and contorted/laminated mudstone layers prevail in the upper part. The transition of facies association is suggestive of the continuous change of main depositional setting from basin plain to lower slope, which could be due to the movement of depocenter by the increase of sediment supply (volcanic activity).

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Journal of Power Electronics
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• v.9 no.2
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.