• Journal of Power Electronics
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• v.14 no.1
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• pp.61-73
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• 2014

Multiphase machines are characterized by high power density, enhanced fault-tolerant capacity, and low torque pulsation. For a voltage source inverter supplied multiphase machine, the probability of load imbalances becomes greater and unwanted low-order stator voltage harmonics occur. This paper deals with the PWM control of multiphase inverters under unbalanced load conditions and it proposes a novel near-five-vector SVPWM algorithm based on the five-phase six-leg inverter. The proposed algorithm can output symmetrical phase voltages under unbalanced load conditions, which is not possible for the conventional SVPWM algorithms based on the five-phase five-leg inverters. The cause of extra harmonics in the phase voltages is analyzed, and an xy coordinate system orthogonal to the ${\alpha}{\beta}z$ coordinate system is introduced to eliminate low-order harmonics in the output phase voltages. Moreover, the digital implementation of the near-five-vector SVPWM algorithm is discussed, and the optimal approach with reduced complexity and low execution time is elaborated. A comparison of the proposed algorithm and other existing PWM algorithms is provided, and the pros and cons of the proposed algorithm are concluded. Simulation and experimental results are also given. It is shown that the proposed algorithm works well under unbalanced load conditions. However, its maximum modulation index is reduced by 5.15% in the linear modulation region, and its algorithm complexity and memory requirement increase. The basic principle in this paper can be easily extended to other inverters with different phase numbers.

• Journal of the Korea Society of Computer and Information
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• v.28 no.2
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• pp.69-75
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• 2023

Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.5
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• pp.88-94
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• 2009

We propose a scheme which reduce the computational complexity of the lattice reduction (LR) aided detector in MIMO system. The performance of the ML detection algorithm is good but the computational complexity grows exponentially with the number of antenna elements and constellation points. LR aided detector shows the same diversity with the ML scheme with relatively less complexity. But the LR scheme still requires many computations since it involves several iterations of size reduction and column vector exchange. We notice that the LR process depends not on the received signal but only on the channel matrix so we can apply LR process offline and store the results in Look-Up Table (LUT). In this paper we propose an algorithm to generate the LUT which require less memory requirement and we evaluate the performance and complexity of the proposed system. We show that the proposed system requires less computational complexity with similar detection performance compared with the conventional LR aided detector.

• Journal of Korea Multimedia Society
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• v.14 no.10
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• pp.1238-1242
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• 2011

An efficient architecture for the reduction of complexity in forward quantization of H.264/AVC is presented in this paper. Since the multiplication operation in forward quantization plays crucial role in complexity of algorithm. More efficient quantization architecture with simplified high speed multiplier is proposed. It uses the modification of the quantization operation and the high speed multiplier is applied for simplification of quantization process.

• ETRI Journal
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• v.34 no.1
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• pp.110-113
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• 2012

We propose a very-low-complexity lattice-reduction (LR) algorithm for multi-input multi-output detection in time-varying channels. The proposed scheme reduces the complexity by performing LR in a block-wise manner. The proposed scheme takes advantage of the temporal correlation of the channel matrices in a block and its impact on the lattice transformation matrices during the LR process. From this, the proposed scheme can skip a number of redundant LR processes for consecutive channel matrices and performs a single LR in a block. As the Doppler frequency decreases, the complexity reduction efficiency becomes more significant.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.51-60
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• 2005

The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.5
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• pp.924-930
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• 2015

In this paper, we propose a novel approach of low computational complexity to improve the speech quality of the small acoustic equipment in noisy environment. The conventional gain control algorithm suppresses the noise of input signal, and then the part of wide dynamic range compression (WDRC) amplifies the undesired signal. The proposed algorithm controls the gain of hearing aids according to speech present probability by using the output of a voice activity detection (VAD). The performance of the proposed scheme is evaluated under various noise conditions by using objective measurement and yields superior results compared with the conventional algorithm.

• ETRI Journal
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• v.30 no.6
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• pp.807-817
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• 2008

We present a low-density parity-check (LDPC)-based, threaded layered space-time-frequency system with emphasis on the iterative receiver design. First, the unbiased minimum mean-squared-error iterative-tree-search (U-MMSE-ITS) detector, which is known to be one of the most efficient multi-input multi-output (MIMO) detectors available, is improved by augmentation of the partial-length paths and by the addition of one-bit complement sequences. Compared with the U-MMSE-ITS detector, the improved detector provides better detection performance with lower complexity. Furthermore, the improved detector is robust to arbitrary MIMO channels and to any antenna configurations. Second, based on the structure of the iterative receiver, we present a low-complexity belief-propagation (BP) decoding algorithm for LDPC-codes. This BP decoder not only has low computing complexity but also converges very fast (5 iterations is sufficient). With the efficient receiver employing the improved detector and the low-complexity BP decoder, the proposed system is a promising solution to high-data-rate transmission over selective-fading channels.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1961-1974
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• 2019

In this letter, a harmonic-mean-based dual-antenna selection scheme at relay node is proposed in two-way relaying networks (TWRNs). With well-designed distributed orthogonal concatenated Alamouti space-time block code (STBC), a dual-antenna selection problem based on the instantaneous achievable sum-rate criterion is formulated. We propose a low-complexity selection algorithm based on the harmonic-mean criterion with linearly complexity $O(N_R)$ rather than the directly exhaustive search with complexity $O(N^2_R)$. From the analysis of network outage performance, we show that the asymptotic diversity gain function of the proposed scheme achieves as $1/{\rho}{^{N_R-1}}$, which demonstrates one degree loss of diversity order compared with the full diversity. This slight performance gap is mainly caused by sacrificing some dual-antenna selection freedom to reduce the algorithm complexity. In addition, our proposed scheme can obtain an extra coding gain because of the combination of the well-designed orthogonal concatenated Alamouti STBC and the corresponding dual-antenna selection algorithm. Compared with the common-used selection algorithms in the state of the art, the proposed scheme can achieve the best performance, which is validated by numerical simulations.