• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.389-393
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• 2003

This paper describes the design of enhanced TSSI RF Power Detector which has wide dynamic range using switch and Log amp. This Power Detector consists of low and high gain loops, and they adaptively switched by output DC voltage which is proportioned to input power level. Because Power Detector needs to separate the channel, so architecture is heterodyne system having 70MHz intermediate frequency. This proposed RF Power Detector is settle to the satisfaction of Closed loop power control system for W-CDMA optic repeater, and the obtained dynamic range cover the higher than 50dB.

• Proceedings of the KOR-KST Conference
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• 1999.10a
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• pp.405-410
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• 1999

• Journal of Electrical Engineering and Technology
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• v.6 no.5
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.737-746
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• 1996

In this paper, we present simulation result of quantization effects about a new Angular From Carrier Recovery Loop(AF CR loop) for PSK modulation technique. AF CR loop includes detected angle symbol and Multi Level hardimiter. In general, detected angle is used in dtermining symbol. Because detected angle is used to make an error signal of phase detector output, hardware implementation of AF CR loop is simpler than that of other loops. Before hardware implementation of AF CR loop, the result due to quantization effect should be investigated. In order to confirm quntization effect of AF CR loop, we evaluate performance of this loop by Monte-Carlosimulation method. Under both in the AWGN and Jake's fading noise channel environments, we confirmed the characteristics of AF CR loop in terms of RMS jitter due to quntization effect. Differential APSK modulation schemeis used in this paper. Especially, Jake's fading channel is used as a channel model and also AGC(Automatic Gain Control) is used in the overall process of performance evaluation. We obtained the resonable result of quantization effect about AF CR loop. With the result of performanceevaluation based on quantization effects, we can expect to operate AF CRloop under the fading channel environments reasonably well.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1129-1132
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• 2003

본 논문에서는 위상/주파수 검출기을 설계시 문제가 되는 Reference Spur을 없게 하여 Low Noise를 구현할 수 있는 No Spike PFD(Phase Frequency Detector)를 제안한다. 위상동기루프의 특별한 형태로 차지 펌프 위상동기루프가 있다. 차지 펌프위상동기 루프는 일반적으로 3-state 위상/주파수 검출기를 이용한다. 이 3-state 위상/주파수 검출기는 기준 신호와 VCO 출력 신호의 위상차에 비례하는 디지털 파형으로 출력을 내보낸다. 차지 펌프 위상동기루프 그림 1 처럼 디지털 위상/주파수 검출기(PFD), 차지 펌프(CP), 루프 필터(LF), VCO로 구성된다. PFD 는 기준 신호와 VCO 에 의해 만들어진 출력 신호를 입력받아 각각의 위상과 주파수를 비교한다. 즉, 출력 신호가 기준 신호보다 느릴 때에는 출력 신호를 앞으로 당기기 위해서 up 신호를 넘겨주고, 출력 신호가 기준 신호보다 빠를 때에는 출력 신호를 뒤로 밀기 위해 down 신호를 넘겨준다. 차지 펌프(CP)의 전류를 Ip 라고 한다면, CP 에서 LF 로 흐르거나, LF에서 CP로 흐르는 전류 Ip의 평균량이 기준 신호와 VCO 출력 신호의 위상차에 비례하는 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.6
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• pp.572-579
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• 1992

In this thesis, feedback circuit and FM detector applied to superheterodyne receiver to extract audio signal without random noise Is implemented. The feedback loop circuit converts 45MHz received signal to 4SiKHz If signal containing mess-age without random noise. Also the feedback loop provides the End local frequency, so narrowband BPF which is containing maximum Doppler frequency without message Is needed. Finally, quadrature FM detector extract audio signal by synthesis o350" shifted signal and ampli-tude limited signal. RSSI characteristics is measured and audio characteristics Is compared with existing If module.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.