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Dynamic Model of Centrifugal Compressor for Prediction of Surge Evolution and Performance Variations (서지 발현과 성능 예측을 위한 원심압축기 동적 거동 모델)

  • Jung, Mooncheong;Han, Jaeyoung;Yu, Sangseok
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.40 no.5
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    • pp.297-304
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    • 2016
  • When a control algorithm is developed to protect automotive compressor surges, the simulation model typically selects an empirically determined look-up table. However, it is difficult for a control oriented empirical model to show surge characteristics of the super charger. In this study, a dynamic supercharger model is developed to predict the performance of a centrifugal compressor under dynamic load follow-up. The model is developed using Simulink$^{(R)}$ environment, and is composed of a compressor, throttle body, valves, and chamber. Greitzer's compressor model is used, and the geometric parameters are achieved by the actual supercharger. The simulation model is validated with experimental data. It is shown that compressor surge is effectively predicted by this dynamic compressor model under various operating conditions.

A Fast Encoding Algorithm for Image Vector Quantization Based on Prior Test of Multiple Features (복수 특징의 사전 검사에 의한 영상 벡터양자화의 고속 부호화 기법)

  • Ryu Chul-hyung;Ra Sung-woong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.12C
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    • pp.1231-1238
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    • 2005
  • This paper presents a new fast encoding algorithm for image vector quantization that incorporates the partial distances of multiple features with a multidimensional look-up table (LUT). Although the methods which were proposed earlier use the multiple features, they handles the multiple features step by step in terms of searching order and calculating process. On the other hand, the proposed algorithm utilizes these features simultaneously with the LUT. This paper completely describes how to build the LUT with considering the boundary effect for feasible memory cost and how to terminate the current search by utilizing partial distances of the LUT Simulation results confirm the effectiveness of the proposed algorithm. When the codebook size is 256, the computational complexity of the proposed algorithm can be reduced by up to the $70\%$ of the operations required by the recently proposed alternatives such as the ordered Hadamard transform partial distance search (OHTPDS), the modified $L_2-norm$ pyramid ($M-L_2NP$), etc. With feasible preprocessing time and memory cost, the proposed algorithm reduces the computational complexity to below the $2.2\%$ of those required for the exhaustive full search (EFS) algorithm while preserving the same encoding quality as that of the EFS algorithm.

FPGA Implementation of a Grant Distribution Algorithm for the MAC in the ATM-PON (ATM-PON에서 MAC을 위한 승인분배 알고리즘의 FPGA 구현)

  • Kim, Tae-Min;Chung, Hae;Shin, Gun-Soon;Kim, Jin-Hee
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.10
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    • pp.1-9
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    • 2001
  • The MAC (Medium Access Control) protocol is needed for the OLT(Optical Line Termination) to allocate bandwidth to ONUs(Optical Network Units) and ONTs(Optical Network Terminations) dynamically in the ATM PON(Passive Optical Network). With the protocol, the OLT gathers ONUs' informations and provides grants efficiently to each ONU. Two important functions of the MAC protocol is the grant request procedure and the grant distribution algrithm. The latter has the greatest arithmetic portion in the TC(Transmission Convergence) module, occupies a relatively large portion of the overall chip area, has often been the limiting factor in terms of speed, and should be designed to guarantee the quality of service for various traffics. In this paper, we implement the MAC with the FPGA which can allocate grants dynamically according to the queue length information and the number of active ONUs and distribute grants uniformly to minimize the cell delay variation for each ONU. The structure of the MAC scheduler for the dynamic bandwidth assignment has a programmable look-up table. Also, it has a simple structure, the less chip area, and the lower delay time.

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A Study on Depth Data Extraction for Object Based on Camera Calibration of Known Patterns (기지 패턴의 카메라 Calibration에 기반한 물체의 깊이 데이터 추출에 관한 연구)

  • 조현우;서경호;김태효
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2001.06a
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    • pp.173-176
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    • 2001
  • In this thesis, a new measurement system is implemented for depth data extraction based on the camera calibration of the known pattern. The relation between 3D world coordinate and 2D image coordinate is analyzed. A new camera calibration algorithm is established from the analysis and then, the internal variables and external variables of the CCD camera are obtained. Suppose that the measurement plane is horizontal plane, from the 2D plane equation and coordinate transformation equation the approximation values corresponding minimum values using Newton-Rabbson method is obtained and they are stored into the look-up table for real time processing . A slit laser light is projected onto the object, and a 2D image obtained on the x-z plane in the measurement system. A 3D shape image can be obtained as the 2D (x-z)images are continuously acquired, during the object is moving to the y direction. The 3D shape images are displayed on computer monitor by use of OpenGL software. In a measuremental result, we found that the resolution of pixels have $\pm$ 1% of error in depth data. It seems that the error components are due to the vibration of mechanic and optical system. We expect that the measurement system need some of mechanic stability and precision optical system in order to improve the system.

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A Study of the Fluidic Characteristics of High-Pressure Fuel Pumps for GDI Engines (GDI 고압펌프의 유동특성에 관한 연구)

  • Lee, Sangjin;Noh, Yoojeong;Liu, Hao;Lee, Jae-Cheon;Shin, Yongnam;Park, Yongduk;Kang, Myungkweon
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.39 no.5
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    • pp.455-461
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    • 2015
  • A high-pressure fuel pump is a key component in a gasoline direct injection (GDI) engine; thus, understanding its flow characteristics is essential for improving the engine power and fuel efficiency. In this study, AMESim, which is a hydraulic analysis program, was used to analyze the performance of the high-pressure fuel pump. However, since AMESim uses a one-dimensional model for the system analysis, it does not accurately analyze the complicated flow characteristics. Thus, Fluent, computational fluid dynamics (CFD) software, was used to calculate the flow rates and net forces at the intake and discharge ports of the high-pressure fuel pump where turbulent flow occurs. The CFD analysis results for various pressure conditions and valve lifts were used as look-up tables for the AMEsim model. The CFD analysis results complemented the AMEsim results, and thus, improved the accuracy of the performance analysis results for the high-pressure fuel pump.

Color decomposition method for multi-primary display using 3D-LUT in linearized LAB space (멀티프라이머리 디스플레이를 위한 3D-LUT 색 신호 분리 방법)

  • Kang Dong-Woo;Cho Yang-Ho;Kim Yun-Tae;Choe Won-Hee;Ha Yeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.6
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    • pp.9-18
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    • 2005
  • This paper proposes the color decomposition method for multi-primary display (MPD) using a 3-dimensional look-up-table (3D-LUT) in a linearized LAB space. The proposed method decomposes conventional three-primary colors into the multi-primary control values of a display device under constraints of tristimulus match. To reproduce images on the MPD, the color signals should be estimated from a device-independent color space, such as CIEXYZ and CIELAB. In this paper, the linearized LAB space is used due to its linearity and additivity in color conversion. The proposed method constructs the 3-D LUT, which contain gamut boundary information to calculate color signals of the MPD. For the image reproduction, standard RGB or CIEXYZ is transformed to the linearized LAB and then hue and chroma are computed to refer to the 3D-LUT. In the linearlized LAB space, the color signals of a gamut boundary point with the same lightness and hue of an input point are calculated. Also, color signals of a point on gray axis are calculated with the same lightness of an input. With gamut boundary points and input point, color signals of the input points are obtained with the chroma ratio divided by the chroma of the gamut boundary point. Specially, for the hue change, neighboring boundary points are employed. As a result the proposed method guarantees the continuity of color signals and computational efficiency, and requires less amount of memory.

A High Speed LDPC Decoder Structure Based on the HSS (HSS 기반 초고속 LDPC 복호를 위한 구조)

  • Lee, In-Ki;Kim, Min-Hyuk;Oh, Deock-Gil;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.2
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    • pp.140-145
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    • 2013
  • This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

Fuzzy Logic PID controller based on FPGA

  • Tipsuwanporn, V.;Runghimmawan, T.;Krongratana, V.;Suesut, T.;Jitnaknan, P.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1066-1070
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    • 2003
  • Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

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An Efficient Integer Division Algorithm for High Speed FPGA (고속 FPGA 구현에 적합한 효율적인 정수 나눗셈 알고리즘)

  • Hong, Seung-Mo;Kim, Chong-Hoon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.2
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    • pp.62-68
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    • 2007
  • This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

Reconstruction of Transmitted Frames for Visual Quality Assessment of Streaming Video (스트리밍 비디오 화질 평가를 위한 수신 영상 복원)

  • Park, Su-Kyung;Sim, Dong-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.1
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    • pp.32-40
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    • 2009
  • In this paper, we proposed an reconstruction algorithm of transmitted frames from displayed image on video terminal. For image quality assessment of the video streaming in the wireless network, we need information of the image that is transmitted to the end-user's device. Generally, subjective methods are widely used to evaluate the image quality by human beings because it is difficult to extract the transmitted image from the end-user's device. This paper presents an image reconstruction algerian based on the displayed image in video terminal for the extraction of the transmitted image. In the proposed method, we acquired the displayed image on video terminal using the camera. Camera-acquired images exhibit geometric and color distortions caused by characteristics of cameras and display devices. Therefore we correct the geometric distortion by exploiting the homography and color distortion by pre-computed look-up table. The experimental results show that the proposed measurement system yields promising estimation performance in terms of PSNR of $27{\sim}28dB$. We also carried out performance evaluation of the proposed method in terms of EPSNR and the quality of the estimated images by the proposed algerian was in fairly good range of MOS test scale.