• 제목/요약/키워드: Lock Time

검색결과 371건 처리시간 0.025초

RM 스케쥴링과 Lock-Free 공유개체에 의한 실시간 시뮬레이션 (The Real-Time Constructive Simulation With the RM scheduling and Lock-free Shared Objects)

  • 박현규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.519-522
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    • 1998
  • The Constructive Battle simulation Model is very important to the recent military training for the substitution of the field training. However, real battlefield systems operate under rea-time conditions, they are inherently distributed, concurrent and dynamic. In order to reflect these properties by the computer-based simulation systems which represent real world processes, we have been developing constructive simulation model for several years. The constructive simulation system is one of the famous real-time system software, nd the one common feature of all real-time systems is defined as the correctness of the system depend not only on the logical result of computation, but also on the time at which the results are produced. Conventionally, scheduling and resource allocation activities which have timing constraints are major problem of real-time computing systems. To overcome these constraints, we elaborated on these issues and developed the simulation system on commercially available hardware and operating system with lock-free resource allocation scheme and rae monotonic scheduling.

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Lock Time 개선과 Jitter 감소를 위한 전하 펌프 PLL (Charge Pump PLL for Lock Time Improvement and Jitter Reduction)

  • 이승진;최평;신장규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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    • pp.2625-2628
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    • 2003
  • Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1%, and the jitter is reduced by 45.2% compared with typical CPPLL.

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항구에 있어서 갑거(문)의 적정규모결정을 위한 대기행열의 모의조작에 관한 연구 (A Study on Queuing Simulation for Determination of Optimun Lock Size)

  • 김순근;김치홍
    • 물과 미래
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    • 제12권1호
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    • pp.60-71
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    • 1979
  • In general, the lock structure is built at place of having great deal range for dealing with effective ships operation such as in the west coast of Korea. In Inchon harbour, the two locks of 10 KT and 50 KT tonnage class in total has been constructed for several years age, however, it has been recorded many waiting vessels at outer harbour due to the increment of oceangoing vessels & shortage of berthing facilities in accordance with beyond expectation of cargo amount increment. This paper attempts to solves the waiting vessels problem at outer harbour by simulation in applying queing theory. It is found that the simulation results such as average queue time, service time, and queue length during lock operation can be applied to find the minimum of the cost function for determination of optimum Lock Size

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진동 유동장에서 유동공진에 의한 실린더 후류의 와류 특성 변화 (Change of Vortex Dynamics in the Cylinder Wake by the Lock-on to Oscillatory Incident Flow)

  • 김원태;성재용;유정열
    • 대한기계학회논문집B
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    • 제27권11호
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    • pp.1645-1654
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    • 2003
  • When vortex shedding is locked-on to a single frequency oscillatory flow, the variations of vortex dynamics are investigated using a time-resolved PIV system. Wake regions of recirculation and vortex formation, dynamic behavior of the shed vortices and the Reynolds stress fields are measured in the wake-transition regime at the Reynolds number 360. In the lock-on state, reduction of the wake region occurs and flow energy distributed downstream moves upstream being concentrated near the cylinder base. To observe the dynamic behavior of the shed vortices, the trajectory of the vortex center extended to the inside of the wake bubble is considered, which describes well the formation and evolution processes. The Reynolds stresses and their contributions to overall force balance on the wake bubble manifest the increase of the drag force by the lock-on.

A Study on the Optimized Test Condition of Lock-in IR Thermography by Image Processing

  • Cho, Yong-Jin
    • 비파괴검사학회지
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    • 제32권3호
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    • pp.276-283
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    • 2012
  • In this study, it was studies the utilization of LIT(lock-in infrared thermography) which can detect defects in welded parts of ship and offshore structures. Quantitative analysis was used through methods of filtering and texture measurement of image processing techniques to find the optimized experimental condition. We verified reliability in our methods by applying image processing techniques in order to normalize evaluations of comparative images that show phase difference. In addition, low to mid exposure showed good results whereas high exposure did not provide significant results in regards to intensity of light exposure on surface. Lock-in frequency was satisfactory around 0.1 Hz regardless of intensity of light source we had. In addition, having the integration time of thermography camera inversely proportional to intensity of exposed light source during the experiment allowed good outcome of results.

THE EFFECT OF MASKED SIGNAL ON THE PERFORMANCE OF GNSS CODE TRACKING SYSTEM

  • Chang, Chung-Liang;Juang, Jyh-Ching
    • 한국항해항만학회:학술대회논문집
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    • 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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    • pp.223-228
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    • 2006
  • The main purpose of this paper is to describe the code tracking performance of a non-coherent digital delay lock loop (DLL) or coherent DLL while tracking GNSS signal in the presence of signal masking. The masking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal masking is used to remove random or periodic interference. Three types of the masked signal are considered - no masking, periodic masking, and random masking of the signal input to the receiver. The mean time to lose lock (MTLL) of the code tracking loop are evaluated, and some numerical result and simulation results are reported. Finally, the steadystate tracking errors on the performance of the tracking loop in interference environment are also presented.

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PHS 어플리케이션에서의 빠른 스위칭 주파수 합성기를 위한 효율적인 Coarse Tuning 방법 (An Efficient Coarse Tuning Scheme for Fast Switching Frequency Synthesizer in PHS Applications)

  • 박도진;정성규;김진경;부영건;정지훈;이강윤
    • 대한전자공학회논문지SD
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    • 제43권9호
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    • pp.10-16
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    • 2006
  • 본 논문에서는 PHS 어플리케이션에서 새로운 Coarse Toning 기법을 사용한 빠른 스위칭의 CMOS 주파수 합성기를 기술하였다. 제안한 Coarse Tuning 방법은 Phase Noise와 Lock-Time을 최적화하기 위해 LC-VCO의 적절한 Tuning Capacitances를 선택하는 것이다. 이를 바탕으로 측정된 Lock-Time은 약 $20{\mu}s$ 이고, Phase Noise는 600kHz의 offset에서 -121dBc/Hz이다. 칩은 $0.25{\mu}m$ CMOS 공정으로 제작하였고, 면적은 $0.7mm{\times}2.1mm$ 이다. 소비전력은 2.7V 공급 전압 하에서 54mW 이다.

위상잠금 열화상 기법의 최적 실험 조건 탐색 연구 (An Exploratory Study on the Optimized Test Conditions of the Lock-in Thermography Technique)

  • 조용진
    • 비파괴검사학회지
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    • 제31권2호
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    • pp.157-164
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    • 2011
  • 위상잠금 적외선 열화상(lock-in infrared thermography) 기법의 조선해양공학 분야에 적용 가능성을 검토하였다. 이를 위해 실험계획법에 의해 향상된 결함부와 건전부의 위상차 대비영상을 얻기 위한 탐색 연구를 수행하였다. 위상차 대비영상의 평가를 정량회하기 위하여 대비 기준표와 홀 크기에 가중치를 주는 방법을 적용하여 유용한 판별기준임을 입증하였다. 그리고 표면에 광 조사 세기는 중간이나 낮은 조사량이 좋은 결과를 보여주고, 높은 조사는 유용한 결과를 주지 못했다. 위상잠금 주파수는 가진 광원의 세기에 비례하여 좋은 결과를 획득할 수 있었고, 열화상 카메라의 노출시간(integration time)은 조사 광원의 세기와 반비례하여 실험을 수행하는 것이 좋은 결과를 얻을 수 있었다. 그러나 시험편(specimen)의 차이는 약간의 편향된 결과를 얻었지만 유의하지는 못했다.

n-$\Delta$ Delay-Lock Loops의 성능 해석 (Performance Analysis of Extended n-$\Delta$ Dely-Lock Loops)

  • 류승문;은중관;김재균
    • 대한전자공학회논문지
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    • 제18권1호
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    • pp.16-24
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    • 1981
  • Delay-lock loop(DLL)는 상단관련이 있는 두 파형 사이의 지연차이를 추적하는한 최적장치이다. 본 논문에서는 지연시간이 n- 로 확장된 한 DLL의 구조와 동기상실 주파수등 저역주파수대의 성능이 해석되었다. 본 DLL은 correlator와 개선된 PN 신호장치로 구성되었으며,상관 특성은 확장된 S-커브의 형태를 가지고 있다. 잡음이 크더라도 추적범위와 초기동기시간이 좋은 특성을 가지고 있다. 3- DLL을 1- DLL과 비교하면 직렬동기방식에서 초기동기시간이 3배나 빠르며, doppler shift에 대한 저항이 2배나 큰 것으로 나타났다.

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스마트폰 기반의 OTP 도어락 시스템 (Smartphone-based OTP Door Lock System)

  • 김진배;오창석;정시영;정상헌;김태용;장원태
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2015년도 추계학술대회
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    • pp.560-563
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    • 2015
  • 기존에 사용되어지는 도어락 시스템은 키 또는 카드, 패드를 이용하는 방식으로 복제, 분실, 훼손 등의 위험과, 타인에게 노출되는 문제점을 가지고 있다. 본 논문에서는 기존의 도어락 시스템 문제점을 보완하고자 스마트폰에 내장된 Bluetooth통신과 OTP(One-Time-Password), Hide-Key 인증방식 및 Arduino를 활용한 스마트폰 기반의 무선 OTP 도어락 시스템 설계 및 구현함으로써 사용자들은 보안 및 노출의 위험성에서 벗어나 보다 편리하고 안전한 생활을 가능하게 한다.

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