• Journal of the Korean Society for Precision Engineering
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• v.21 no.4
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• pp.72-78
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• 2004

In this paper, a development of an inductive position sensor is described. The sensor is similar to a radial magnetic bearing in that the sensor stator is shaped like a heteropolar magnetic bearing and is driven by a switching amplifier. A demodulation filter extracts the gap information from the switching current ripples. A prototype sensor exhibits the resolution of $0.43\mum$ and the dynamic bandwidth of about 800Hz. The dynamic performance can be improved by increasing the switching frequency. However, the eddy current effects become noticeable at high switching frequency, thus limiting the improvement of the bandwidth.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.521-524
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• 1990

There is an increasing interest in high-speed signal processing in modern telecommunication and consumer electronics applications. HDTV, ISDN. A limiting factor in Op-Amp based analog integrated circuits is the limited useful frequency range. This research program will develop a new CMOS Op-Amp architecture with improved gainband width product. The new design CMOS Op-Amp will achieve up to 100MHz unity gainband width with a 1.5-micron design rule.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.705-711
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• 2004

We propose novel OCDMA system with the structure of reconfigurable may encoder/decoder(RAE/ RAD), which are able to reallocate the 2-D optical codes to each subscriber and recover the transmitted data at all the receiving nodes. We have first implemented the double hard limiters composed of limiting amplifier(first hard limiter) that maintain a level of the encoded data from receiving node and AND detector(second hard limiter) for detecting the position of the encoded data and recovering the data. With the proposed system, it was successfully implemented to recover a specific channel data out of 16 code-multiplxed channels using FPGA and 4 DFB-LDs having distinct wavelengths. From experimental results, the code length resulted from increasing the number of the simultaneously connected channels has been reduced by using 2-D OCDMA multiplexed in time and wavelength instead of 1-D OCDMA. In addition, bit errors phenomenon on account of deterioration of autocorrelation peak-to-side lobe ratio is enhanced by using the double hard limiters composed of AND detector and limiting amplifiers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.552-560
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• 2017

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.164-175
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• 1997

In this paper, the CE-OQPSK that has constant envelope was designed for applying PSK to the nonlinear amplifier so as to improve power efficiency. For this realization. ROM and D/A converter that have relative low power consumption were used. As a result of comparing the PSD (Power spectrum density) of CE-OQPSK with that of conventional OQPSK through simulation for estimating the performance. In case of correlation factor ${\alpha}$ = 0.707. the improvement of bandwidth efficiency of 5% and 20% is achieved in the main lobe and the sidelobe, respectively. And, in case additional bandwidth-limiting-filter is added, it can be shown that the PSD of CE-OQPSK meet the FCC wireless LAN spectrum specification.

• ETRI Journal
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• v.35 no.2
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• pp.245-252
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• 2013

In this work, we study the physical layer solutions for 10-gigabit-capable passive optical networks (PONs), particularly for an optical link terminal (OLT) including a 10-Gbit/s electroabsorption modulated laser (EML) and a 2.5-Gbit/s burst mode receiver (BM-Rx) in a novel bidirectional optical subassembly (BOSA). As unique features, a bidirectional mini-flat package and a 9-pin TO package are developed for a 10-gigabit-capable PON OLT BOSA composed of a 1,577-nm EML and a 1,270-nm avalanche photodiode BM-Rx, including a single-chip burst mode integrated circuit that is integrated with a transimpedance and limiting amplifier. In the developed prototype, the 10-Gbit/s transmitter and 2.5-Gbit/s receiver characteristics are evaluated and compared with the physical media dependent (PMD) specifications in ITU-T G.987.2 for XG-PON1. By conducting the 10-Gbit/s downstream and 2.5-Gbit/s upstream transmission experiments, we verify that the developed 10-gigabitcapable PON PMD prototype can operate for extended network coverage of up to a 40-km fiber reach.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.6
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• pp.1058-1063
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• 2010

In this paper, we designed self-frequency synchronizing circuit using image rejection mixer(IRM) and single-sideband(SSB) up-converter which can effectively eliminate the image frequencies occurred in multi-channel super-heterodyne receivers and help us to match inter-channel phase. Also the self-frequency synchronizing circuit simplifies system because there need no extra devices for making intermediate frequency(IF) by creating the local signal within several nanoseconds by means of generating the same frequency of IF signal and modulating radio frequency(RF) signal. We adopt the limiting amplifier for the purpose of protecting the circuit from spurious signals which come from the front end side having wide instantaneous bandwidth characteristics and constantly injecting same level into the input local signal of IRM. The IRM we fabricated has image rejection ratio of 27dB, which is good over 7dB for foreign company's. Also, the SSB up-converter we fabricated has 1dB compression point of 18dBm, which is good over 16dB for foreign company's. And the size is compact about one-forth.