• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.45-53
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• 1999

A pre amplifier, a limiting amplifier, and a decision IC chipset for 10Gbit/s optical receiver was implemented with AIGaAs/GaAs HBT(Heterojunction Bipolar Transistor) technology. The HBT allows a cutoff frequency of 55GHz and a maximum oscillation of 45GHz. An optical receiver front-end was implemented with the fabricated pre amplifier IC and a PIN photodiode. It showed 46dB$\Omega$, gain and $f_{3db}$ of 12.3GHz. The limiting amplifier Ie showed 27dB small signal gain, $f_{3db}$ of 1O.6GHz, and the output is limited to 900mVp-p from 20mVp-p input voltage. The decision circuit IC showed 300-degree phase margin and input voltage sensitivity of 47mVp-p at 1OGbit/s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.353-356
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• 1996

Ultra-high-speed analog and digital ICs (integrated circuits) fur 10Gbit/sec optical communication systems have been designed, fabricated and analyzed in this research. These circuits, which are laser diode (LD) driver, pre-amplifier, automatic gain controlled (AGC) amplifier, limiting amplifier and decision circuit, have been implemented with AIGaAs/GaAs heterojunction bipolar transistors (HBTs). The optimized AIGaAs/GaAs HBTs for the 10Gbps circuits in this work showed the cutoff and maximum oscillation frequencies of 65㎓ and 53㎓, respectively. It is demonstrated in this paper that the 10Gbps optical communication system can be realized with the ICs designed and fabricated using AlGaAs/GaAs HBTs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.13-19
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• 2006

A 5Gb/s cross coupled transimpedance amplifier (TIA) & limiting amp(LA), regulated cascode(RGC) is realized in a 0.18$\mu$m CMOS technology for optical printed circuit board applications. The optical receiver demonstrates $92.8db{\Omega}$ transimpedance and limiting amplifier gain, 5Gb/s bandwidth for 0.5pF photodiode capacitance, and 9.74mW power dissipation from 1.8V, 2.4V supply. Input stage impedance is $50{\Omega}$. The circuit was implemented on an optical PCB, and the 5Gb/s data output signal was measured with a good data eye opening.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.241-244
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• 2012

In this paper, three types of optical receivers are designed using a $0.35-{\mu}m$ standard CMOS technology for plastic optical fiber (POF) applications. Basic common-source transimpedance amplifier (CS-TIA), common-gate TIA (CG-TIA), and regulated-cascode TIA (RGC-TIA) are optimally designed, and their transimpedance gain (TZ gain), 3-dB bandwidth, and noise characteristics are compared and analyzed. As a result of simulations, the RGC-TIA indicates better TZ gain and 3-dB bandwidth than other topologies, and CS-TIA has the best noise performance. Each optical receiver occupies area of $0.35mm^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.79-82
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• 2017

In this paper, we proposed the wireless communication system using millimeter-wave envelope detector. The sub-harmonic mixer based on schottky barrier diode was used in the transmitter. The receiver was used millimeter-wave envelope detector. The transmitter was composed of schottky diode sub-harmonic mixer, frequency tripler, and horn antenna. The receiver was composed of horn antenna, millimeter-wave envelope detector, low pass filter, base band amplifier, and limiting amplifier. At 1.485 Gbps and 300 GHz, the eye-diagram showed a very good performance as measured by the error free. Communication distance is reduced compared to the heterodyne receiver, but compact and lightweight is possible.

• Journal of the Korea Institute of Military Science and Technology
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• v.11 no.5
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• pp.5-11
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• 2008

Recently developed radars use the solid-state power amplifier to amplify the RF signal. The stability of RF signal directly depends on that of the electric power. So the stable and reliable electric power should be needed. When the electric power switch is tuned on for the first time in order to operate the radar system, the in-rush current is generated because of the capacitive characteristic. The excess in-rush current breaks the element. Therefore, the analysis about the in-rush current to design the electric power system is necessary. In this paper, modeling and simulation on the whole power system is carried out and the necessity of limiting the in-rush current is verified. After the analysis, the circuit to limit the in-rush current is designed and examined to verify the analysis. The circuit is good enough to limit the in-rush current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.405-410
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• 2012

This paper presents an inductorless 8-Gb/s adaptive passive equalizer with low-power consumption and small chip area. The equalizer has a tunable RC filter which provides high-frequency gain boosting and a limiting amplifier that restores the signal level from the filter output. It also includes a feedback loop which automatically adjusts the filter gain for the optimal frequency response. The equalizer fabricated in $0.18-{\mu}m$ CMOS technology can successfully equalize 8-Gb/s data transmitted through up to 50-cm FR4 PCB channels. It consumes 6.75 mW from 1.8-V supply voltage and occupies $0.021mm^2$ of chip area.

• ETRI Journal
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• v.30 no.2
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• pp.249-254
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• 2008

In this paper, we demonstrate an electrically band-limited carrier-suppressed return-to-zero (EB-CSRZ) signal generator operating up to a 10 Gbps data rate comprising a single-stage Mach-Zehnder modulator and a wideband signal mixer. The wideband signal mixer comprises inverter stages, a mixing stage, and a gain amplifier. It is implemented by using a 0.13 ${\mu}m$ CMOS technology. Its transmission response shows a frequency range from DC to 6.4 GHz, and the isolation response between data and clock signals is about 21 dB at 6.4 GHz. Experimental results show optical spectral narrowing due to incorporating an electrical band-limiting filter and some waveform distortion due to bandwidth limitation by the filter. At 10 Gbps transmission, the chromatic dispersion tolerance of the EB-CSRZ signal is better than that of NRZ-modulated signal in single-mode fiber.