• Journal of KIBIM
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• v.7 no.4
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• pp.8-20
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• 2017

When it comes to set up the BIM through the reverse engineering, the level of detail(LoD) required for finalized outcomes is different from each purpose. Therefore, it is necessary to establish some concrete criteria which describe the definition of LoDs on 3D modeling for the purpose of each reverse engineering. This research shows the criteria of the 1) positional accuracy, 2) generalization level, 3) scale level, 4) scope of description, and 5) the area available for application by classifying LoD from 1 to 6 on 3D modeling for each purpose of reverse engineering. Moreover, through applying those criteria for the 3D point cloud dataset of building made by terrestrial LiDAR, this research finds out the working hour of 3D modeling of reverse engineering by each LoDs according to defined LoD criteria for each level. It is expected that those findings, how those criteria of LoD on reverse engineering are utilized for modeling-workers to decide whether the outcomes can be suitable for their budget, applicable fields or not, would contribute to help them as a basic information.

• Structural Engineering and Mechanics
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• v.38 no.4
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• pp.429-441
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• 2011

In large-scale problem, a huge size of computational resources is needed for a reliable solution which represents the detailed description of dynamic behavior. Recently, eigenvalue reduction schemes have been considered as important technique to resolve computational resource problems. In addition, the efforts to advance an efficiency of reduction scheme leads to the development of the multi-level system condensation (MLSC) which is initially based on the two-level condensation scheme (TLCS). This scheme was proposed for approximating the lower eigenmodes which represent the global behavior of the structures through the element-level energy estimation. The MLSC combines the multi-level sub-structuring scheme with the previous TLCS for enhancement of efficiency which is related to computer memory and computing time. The present study focuses on the implementation of the MLSC on the direct time response analysis and the frequency response analysis of structural dynamic problems. For the transient time response analysis, the MLSC is combined with the Newmark's time integration scheme. Numerical examples demonstrate the efficiency of the proposed method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.1
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• pp.1-4
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• 1977

In the description and design of certain kinds of sequential machines, we often meet inadequacies of traditional models we adopt to use. To Lessen these inconveniencies, this paper aims to define polymachine as a new basic model of sequential machine. Polymachine, defind on the level of state model, is composed of an index which is and independent componet and a polymer which, as a dependent component, consists of many element machines. In the meantime, some basic characters of the machine are illustrated and discussed in detail, in order to present the usefulness of polymachine.

• Journal of the Korean Operations Research and Management Science Society
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• v.10 no.2
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• pp.1-14
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• 1985

This problem of product selection and princing are considered in congested and uncongested markets. In a congested market, such as a computer service market, product quality (the level of congestion) is partly a function of the amount of usage, which in turn depands on user choice. In an uncongested market, product qualities are set solely by providers. A model of quality and capacity variation is developed using a state equation description to represent user optimizing behavior. The model is used to study the problem of scarce resources among competing user demands through quality-dependent pricing.

• Journal of Korean Library and Information Science Society
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• v.1
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• pp.53-67
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• 1974

This study aims at diagnozing the existing school library laws and their enforcement regulations together with the library organization, and finding out any problems in them for the lack of legal and administrative suppxt has been considered the main hindrances to the developrnent of school library. The results of the work are as follows: 1. Full use of materials on the part of students is impossible because there is description in the school facilitier enforcement regulations except that of reading room. 2. No administrative consederation on the school library. 3. No incentive to be an able librarians because there is no devision in the lebrary teacher eligibility between the elementary and secondary level.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.302-305
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• 2000

This paper proposed an optimal register resource allocation algorithm using graph coloring for minimal register at high level synthesis. The proposed algorithm constructed interference graph consist of the intermediated representation CFG to description VHDL. and at interference graph fur the minimal select color selected a position node at stack, the next inserted spill code and the graph coloring process executes for optimal register allocation. The proposed algorithm proves to effect that result compare another allocation techniques through experiments of bench mark.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.93-96
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• 2002

It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.427-428
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• 2008

본 논문에서는 IEEE 802.11 MAC Layer의 Reception, Transmission 검증을 위해 PLI (Programing Language Interface)를 이용한 방법을 제안한다. PLI를 이용한 검증은 시스템 Level의 검증으로써 설계단계에서 문제점을 확인하고 수정할 수 있다. 그러므로 불필요한 개발비의 낭비를 줄일 수 있고 개발 기간 단축의 효과를 거둘 수 있다. 검증을 위해 Mentor Graphics 사의 HDL (Hardware Description Language) 시뮬레이터인 Modelsim 6.1g Version을 사용하고 PLI를 이용하여 검증 환경을 구축한다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.659-661
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• 1988

SPM is MDC Processor for string pattern expressed in directional chain code. In this paper we consider the string pattern matching algorithm (Leve-nstein Algorithm) whitch is portion of Dynamic Programing, and propose architecture of SPM and simulate it on the R-T level to evaluate its architecture. We used the C language as the hardware description language, and developed it on the IBM PC/AT Zenix system V OS environment.