• 한국통신학회논문지
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• 제29권7B호
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• pp.711-721
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• 2004

To provide the end-to-end service differentiation for assured services, the random early demotion and promotion (REDP) marker in the edge router at each domain boundary monitors the aggregate flow of the incoming in-profile packets and demotes in-profile packets or promotes the previously demoted in-profile packets at the aggregate flow level according to the negotiated interdomain service level agreement (SLA). The REDP marker achieves UDP fairness in demoting and promoting packets through random and early marking decisions on packets. But, TCP fairness of the REDP marker is not obvious as fur UDP sources. In this paper, to improve TCP fairness of the REDP marker, we combine a dropper with the REDP marker. To make packet transmission rates of TCP flows more fair, at the aggregate flow level the combined dropper drops incoming excessive in-profile packets randomly with a constant probability when the token level in the leaky bucket stays In demotion region without incoming demoted in-profile packets. It performs a dropping in the demotion at a domain boundary only if there is no prior demotion. The concatenate dropping at multiple domains is avoided to manifest the effect of a dropping at a domain boundary on TCP fairness. We experiment with the REDP marker with the combined dropper using ns2 simulator for TCP sources. The simulation results show that the REDP marker with the combined dropper improves TCP fairness in demoting and promoting packets by generating fair demoted in-profile traffic compared to the REDP marker. The effectiveness of the selected drop probability is also investigated with showing its impact on the performance of the REDP marker with the combined dropper.

• 한국통신학회논문지
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• 제22권4호
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• pp.855-869
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• 1997

In this paper, we proposed two kids of dynamic priority control mechanisms controlling the cell service ratio in order to improve the QOS(Quality of Service). We also analyse theoretically the characteristics of cell loss probability and mean cell delay time by applying the proposed priority control mechanisms to ATM switch with output buffer. The proposed priority control mechanisms have the same principles of storing cells into buffer but the different principles of serving cells from buffer. The one is the control mechanism controlling the cell service ratio according to the relative cell occupancy ratio of buffer, the other is the control mechanism controlling the cell service ratio according to both the relative cell occupancy ratio of buffer and the average arrival rate. The two service classes of our concern are the delay sensitive class and the loss sensitive class. The analytical results show that the proposed control mechanisms are able to improve the QOS, the characteristics of cell loss probability and mean cell delay time, by selecting properly the relative cell occupancy ratio of buffer and the average arrival rate. conventional DLB algorithm does not support synchronous cells, but the proposed algorithm gives higher priority to synchronous cells. To reduce synchronous cell loss rate, the synchronous cell detector is used in the proposed algorithm. Synchronous cell detector detects synchronous cells, and passes them cells to the 2nd Leaky-Bucket. So it is similar to give higher priority to synchronous cells. In this paper, the proposed algorithm used audio/video traffic modeled by On/Off and Two-state MMPP, and simulated by SLAM II package. As simulation results, the proposed algorithm gets lower synchronous cell loss rate than the conventional DLB algorithms. The improved DLB algorithm for multimedia synchronization can be extended to any other cells which require higher priority.

• 한국인터넷방송통신학회논문지
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• 제19권1호
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• pp.63-68
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• 2019

최근 들어 스마트 팩토리, 차량 내 통신망, 광대역 전력망 등 다양한 응용분야에서 단대단 네트워크 지연시간(End-to-end network delay)에 대하여 엄격한 제한(bound)을 요구하고 있다. 이에 따라 기존 Integrated Services (IntServ) 프레임워크에서의 플로우 기반 스케줄러를 바탕으로 하는 해법들이 다시 제안되고 있다. 하지만 많은 수의 플로우를 구분하여 스케줄 하는 것은 복잡도가 커서 구현하기 어렵다. 차선책인 Class기반 스케줄러는 노드를 지나면서 burst가 기하급수적으로 커지기 때문에 지연시간을 제한하기 어렵다. 이에 따라 트래픽 regulator와 class 기반 스케줄러를 앞뒤로 배치하여 burst의 크기를 줄이면서 동시에 스케줄러의 복잡도를 낮추려는 연구가 등장하고 있다. 본 연구에서는 이러한 regulator와 스케줄러가 하나의 서버에서 간단히 구현되는 방안을 제시하고 성능을 분석하여 대규모 네트워크에서도 수 ms 이내의 최대 delay를 보장함을 보였다.