• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.657-658
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• 2005

We designed 10bit source driver LSI, then the high color depth and the low power consumption are realized thru it. It is adopted mini-LVDS receiver with high speed data transmission and good data recovery performance, Hybrid type DAC to reduce decoder size and OP-AMP with low power consumption and high slew rate. In addition we show our results of the 10-bit gray scale TFT-LCD source driver for 42inch diagonal size and WXGA resolution TFT-LCD TV applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1081-1085
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• 2009

We have already developed EMI reducing techniques using lossless compression by vertically differential EMI suppression method (VDE[1]). It applies lossless modulo reduction and data bit mapping optimization for low voltage differential signaling (LVDS) transmission lines, that reduces the probability of transient bit and EMI by 12 dB [6][7]. We also improved and optimized the VDE for low power LCD interface. With this modified VDE algorithm[8], the developed FPGA was measured the reduction of the power consumption of LCD circuit by more than 15 % compared to the conventional methods in the case of 14-in LCD with SXGA resolution. The VDE algorithm is based on the total image systematic approach. In the VDE method, the present image signals are subtracted for the 1H delayed image signals and transferred to a column driver through a PCB. As the vertical correlations for image signals are very high, we expected that most of the vertically subtracted image signals remain 0 level and transient cycles become very long. As a result, the power consumption and EMI are extremely reduced for the transferred image signals on a PCB. In this paper, we discussed our proposed method by emphasizing the fact that systematic approach are important based on not only display point of view but also total system point of view.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.184.2-184.2
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• 2012

위성의 전장품은 전기적 접속을 위해서 1:1 연결을 하는 Point-to-Point 버스 방식과 여러개의 Slave (Remote Terminal)을 갖고, 일반적으로 1개의 Master (Controller)에 의해서 연결하게 되는 버스 구조를 갖는 접속 채널을 통해서 연결이 된다. 가장 많이 사용되는 방식인 MIL-STD-1553B는 데이터 전송속도가 1Mbps이고, Transformer에 의해서 완전하게 버스와 각 전장품이 완전하게 절연이 되는 구조로, 전기적 고장이 전달되는 것을 방지할 수가 있지만, 설계의 난이도가 높다. 고속 버스는 SpaceWire를 사용하고, 100Mbps이상의 속도를 지원할 수가 있지만, LVDS등의 고속 채널 설계 및 노이즈에 민감한 특성 때문에, 저속의 통신채널에서는 사용하기 어렵다. 저속의 데이터 채널을 위해서는 UART 방식이 사용된다. UART 방식은 RS-422 방식과 RS-485 방식이 사용되지만, 1553B 또는 SpaceWire 등과 같이 프로토콜이 정해지지 않아서, 사용자가 직접 프로토콜을 지정해야하는 문제가 있다. 또한 RS-422은 1:1 방식의 Point-to-Point UART를 위해서 사용되고, RS-485는 버스 방식의 연결을 지원할 수가 있지만, 동시에 여러개의 TX가 enable되는 경우에는 TX사이에 고장을 일으킬 수 있어서, 1번에 TX가 1개만 사용되도록 제어할 필요가 있다. 또한 RS-485방식의 버스를 구현할 경우에는 1553B처럼 와전하게 절연이 불가능하므로, 전기적이나 기능적으로 485버스에 문제가 발생할 경우에 절연과 같은 기능이 지원되도록 구현이 되어야 한다. 본 논문에서는 안정적인 485 UART버스 구현을 위한 기술에 대해서 평가하고 분석하도록 하겠다.

• International Journal of Computer Science & Network Security
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• v.23 no.3
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• pp.94-100
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• 2023

The primary goal of any communication spacecraft is to provide communication in variety of frequency bands based on mission requirements within the Indian mainland. Some of the spacecrafts operating in S-band utilizes a 6m or larger aperture Unfurlable Antenna (UFA for S-band links and provides coverage through five or more S-band spot beams over Indian mainland area. The Unfurlable antenna is larger than the satellite and so the antenna is stowed during launch. Upon reaching the orbit, the antenna is deployed using motors. The deployment status of any deployment mechanism will be monitored and verified by the telemetered values of micro-switch position before the start of deployment, during the deployment and after the completion of the total mechanism. In addition to these micro switches, a camera onboard will be used for capturing still images during primary and secondary deployments of UFA. The proposed checkout system is realized for validating the performance of the onboard camera as part of Integrated Spacecraft Testing (IST) conducted during payload checkout operations. It is designed for acquiring the payload data of onboard camera in real-time, followed by archiving, processing and generation of images in near real-time. This paper presents the architecture, design and implementation features of the acquisition, processing and Image generation system for Camera onboard spacecraft. Subsequently this system can be deployed in missions wherever similar requirement is envisaged.

• Journal of Satellite, Information and Communications
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• v.7 no.3
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• pp.145-148
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• 2012

In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold typedisplay mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by turn on-off backlight, and we realized the ratio of Back Light on-off time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional CCFL (cold cathode fluorescent lamp) cannot follow fast on-off speed, so we evaluated new fluorescent substances of light source to improve residual light characteristic of CCFL. We realized articulate image generation similar to CRT by CCFL blinking drive and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.59-64
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• 2007

This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). We propose a new V-I converter which is insensitive to the power supply variation when it is applied to the TCON. The new V-I converter compensated the output frequency of VCO by appling the current that is inversely proportional to the voltage variation. The proposed idea is implemented with a 1-ploy 3-metal 0.25m TSMC CMOS technology and has the output frequency range from 192MHz to 360MHz at the supply voltage of 2.5V. Measurement result shows the RMS jitter of 100ps in the above output frequency range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.15-22
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• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.34-43
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• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1379-1385
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• 2009

We propose a low-power and high-speed client receiver for a mobile display digital interface (MDDI) newly in this paper. The low-power receiver is designed such that bias currents, sink and source currents, are insensitive to variations of power supply, process, temperature, and common-mode input voltage (VCM) and is able to operate at a rate of 450Mbps or above under the conditions of a power supply range of 3.0 to 3.6Vand a temperature range of -40 to 85$^{\circ}$C. And it is confirmed by a simulation result that the current dissipation is less than 500${\mu}$A. A test chip is manufactured with the Magna chip 0.35${\mu}$m CMOS process. When a test was done, the data receiver and data recovery circuits are functioning normally.