• International Journal of Advanced Culture Technology
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• v.8 no.2
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• pp.42-47
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• 2020

This study is to develop Korean version of the 7 Learning Style Inventory(LSI) for IT major Students by systematic translation process and to test learning style of IT major University students. Translated and developed Korean version of LSI was verified of validity by comparing with existing V.A.K. learning style model. We can develop various tactics for 7 learning styles of students. Once the learning style of each student is confirmed, customized teaching for individual and team can be done more efficiently through teaching and learning strategies according to each learning style. Developed LSI was applied to the IT major students of two classes from Chungwoon University in Incheon. Results of LSI survey show that learning styles of 24 students out of 35 students from two classes are matched with V.A.K. learning styles of same students. It was 68.6% match in learning style, and shows that validity of 7 LSI. We need to elaborate Korean questionnaires of the LSI more, and extend and apply to the non-IT major students group.

• IE interfaces
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• v.16 no.3
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.2
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• pp.34-39
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• 1976

The purpose of this thesis is to make clear the problems which would arisc from the process of making the Minicomputer by the employment of LSI, and to examine a solution to the problems. This Simulation 19 do for value performance of NOVA Emulator which designed before this. As a result of this studies, The problem of the hardware design by Microprocessor, the problem to be accompanied with application of LSI to the computer in the furture, etc. are mentioned definitely.

• Composites Research
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• v.30 no.2
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• pp.77-83
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• 2017

Liquid silicon infiltration, which is one of the methods of producing fiber reinforced ceramic composites, has several advantages such as low fabrication cost and good shape formability. In order to confirm LSI process feasibility of SiC fiber, $SiC_f/SiC$ composites were fabricated using three types of SiC fibers (Tyranno SA, LoxM, Tyranno S) which have different crystallinity and oxygen content. Composites that were fabricated with LSI process were well densified by less than 2% of porosity, but showed an obvious difference in 3-point bending strength according to crystallinity and oxygen content. When composites in LSI process was exposed to a high temperature, crystallization and micro structural changes were occurred in amorphous SiOC phase in SiC fiber. Fiber shrinkage also observed during LSI process that caused from reaction in fiber and between fiber and matrix. These were confirmed with changes of process temperature by SEM, XRD and TEM analysis.

• ETRI Journal
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• v.25 no.5
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.95-96
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• 2006

CMOS Image Sensor(CIS) 소자에서 광감도의 향상과 천연색 형성을 위하여 적용하고 있는 Color-Filter 공정에서 국부적으로 발생하는 strip성 불량과 막질손상을 제거하기 위한 연구를 진행하였다. 우선 지역적 경향성을 보이는 불량에 대해서는 PR strip process type을 액조 진행방식에서 회전식으로 변경했을 때 제거됨을 확인하였고, 막질손상을 최소화하기 위해서는 새로운 유기용매의 적용이 필요하였다. 실험 결과, 케톤기를 가지는 화합물과 Polar Apotic 용매의 혼합화합물을 적용하였을 때 각 막질에 attack을 최소화하면서 원하는 PR만 선택적으로 제거 되며 미세잔류성분에 대한 제거력도 향상됨을 확인하였다.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.99-104
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• 1994

This paper proposes the method to process many pattern data 2-dimensionally at high speed in designing the physical of LSI. And this study shows that the switching network,which transmits pattern data between memory and processing elements at high speed on bidirection,has been designed using the barrel shifter and simulated with VHDL design system.