• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.662-665
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• 2002

This paper describes a novel converter to implement high-speed binary-to-residue conversion for moduli 2$^{n}$ - 1, 2$^{n}$ , 2$^{n}$ +2$^{\alpha}$/($\alpha$$\in$｛0,1,…,n-1｝) without using look-up table. In our implementation, the high-speed converter can be achieved, because of the modulo addition time is independent of the word length of operands by using the Signed-Digit (SD) adders inside the modulo adders. For a LSI implementation of residue SD number system with ordinary binary system, the proposed binary-to-residue converter is the efficient circuit.cient circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.48-54
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• 1982

In the university IC laboratory we can use only a limited number of experimental arrangements. Since practical process parameters determine the fundamental design rules of ICs, appropriate fabrication process must be construtced. Examples of the process to train the engineering students in two or three weeks will be shown.

• Journal of the KSME
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• v.20 no.1
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• pp.64-66
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• 1980

전자업계에서는 그동안 LSI(Large Scale Integrated Circuit), Microprocessor등의 괄목한 개발로 각종 생산공장, 의료기구등의 측정, 가공, 제어 및 계산의 자동화를 가속 시켜주고 있으며 이러한 컴퓨터기능의 범용화로 우리 생활면에도 많은 변화를 가져오고 있다. 계산기의 대중보급화로 계산자(Slide Rule)가 없어지고 조그마한 계산기가 프로그램의 능력을 가짐으로서 통계는 물론, 수학에서는 편미분 방정식 까지도 쉽게 처리해 주며, 기계분야에서는 Beam의 계산, 사절기 구(Four Bar Mechanism)등도 쉽게 풀어주고 있다. 또한 토목분야 에서는 과거 숙달된 측정기 사에 의존하던 지형의 정밀측정이 측정의 자동화로 측정치가 정확하게 읽혀지고 있지만, 반면 아쉬운 점이라면 정밀측정사에 의존하던 정밀도등이 장비의 정밀도에 의존해 가는 경향도 무시 될 수 없겠다. 또한 안과에서는 과거에 시력측정표를 일정거리에 떨어져서 측정하던 시력검사가 이제는 기계를 안구에 대고 자동측정 하게 된 점 등 다 나열 할 수 없게된 현실이다. 그러면 우리 기술인 주변에는 어떠한 면들이 바뀌었는가, 우선 생산 Line의 자동화, 설계자체도 컴퓨터를 이용하는 많은 여건상의 변화가 일어나고 있다. 여기서 선진국등의 현황과 더불어 우리의 여건 진로 방향등을 잠시 고찰해 보고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.251-259
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• 2010

We proposed a tail function parameter extraction procedure for the establishment of a robust ion implantation database. We showed that, for the expression of ion implantation profiles, there are many local minimum values set for the third and fourth moment parameters of $\gamma$ and $\beta$ for the Pearson function that comprises the standard dual Pearson and tail functions. We proposed the use of a joined tail function as a mediate function to extract $\gamma$ and $\beta$, and demonstrated that this enables us to extract the parameters uniquely. Other parameters associated with channeling phenomena can also be simply and uniquely extracted by our procedure.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.64-64
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• 2003

고집적화된 시스템 LSI 반도체 소자 제조 공정에서 소자의 고속화 및 고성능화에 따른 배선층수의 증가와 배선 패턴 미세화에 대한 요구가 갈수록 높아져, 광역평탄화가 가능한 STI CMP(Shallow Trench Isolation Chemical-Mechanical-Polishing)공정의 중요성이 더해가고 있다. 이러한 STI CMP 공정에서 세리아 슬러리에 첨가되는 계면활성제의 농도에 따라 산화막과 질화막 사이의 연마 선택비를 제어하는 것이 필수적 과제로 등장하고 있다. 일반적인 CMP 공정에서 압력 증가에 따른 연마 제거량이 Prestonian 거동을 나타내는 반면, 연마 입자의 크기를 변화시켜 계면활성제의 농도를 달리 하였을 경우, 압력 변화에 따라 Non-Prestonian 거동이 나타나는 것을 고찰할 수 있었다. 따라서 본 연구에서는 세리아 슬러리 내에 첨가되는 계면활성 제의 농도와 연마입자의 크기를 달리한 후, 압력을 변화시킴으로 나타나는 non-Prestonian 거동에 미치는 영향에 대하여 연구하였다.

• Journal of the Korean Society of Safety
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• v.14 no.3
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• pp.69-77
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• 1999

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipment need to be more alert to the problem of electrostatic discharges(ESD). Semiconductor devices such as IC, LSI, VLSI become a high density pattern of being more fragile by ESD phenomena. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the electrostatic discharge sensitive devices. Accordingly, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated to evaluate the ESD phenomina in the semiconductors in this paper. The required data are obtained by Static Honestmeter. Also The results in this paper can be used for the prevention of semiconductor failure by ESD.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1864-1872
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• 2014

Maloperation of protective relays is one of the major causes for cascading tripping in WANS. Another line trip followed by a previous line trip may occur due to overloading of the line, because of the load redistribution or unwanted trip of a backup relay due to change in the flow of fault current. Evaluation of each line is required by considering both of these effects. A new index named Line Security Index (LSI) is proposed in this paper which combines both Vulnerability Index (VI) and Protectability Index (PI) to completely evaluate the security of individual lines and their importance in the power grid. Computer simulations have been performed on the Korean power grid data to establish the feasibility of the proposed idea.