• Title/Summary/Keyword: LSI

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The Evolution of the Science of Immunotoxicology: From a Mechanistic Foundation to Regulatory Applications

  • Holsapple, M.
    • Proceedings of the Korea Society of Environmental Toocicology Conference
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    • 2002.10a
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    • pp.93-104
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    • 2002
  • The overall objective of this lecture will be to present an overview of the evolution of the science of immunotoxicology by highlighting a few key milestones, namely a solid mechanistic foundation and recent applications in a regulatory context. Neither time nor space will allow a discussion of the full extent of the evolution of immunotoxicology from a historical perspective.

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The structure of ATM Switch with the Shared Buffer Memory and The Construction of Switching Network for Large Capacity ATM (대용량 ATM을 위한 공유 버퍼 메모리 스위치 구조 및 교환 망의 구성 방안)

  • 양충렬;김진태
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.1
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    • pp.80-90
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    • 1996
  • The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

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The implementation of a low-power-consumptive OFDM LSI for the high speed indoor wireless LAN (구내용 고속무선LAN설비를 위한 저전력형 OFDM LSI구현에 관한 연구)

  • 차재상;김성권
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.16 no.5
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    • pp.66-74
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    • 2002
  • OFDM(Orthogonal Frequency Division Multiplexing)is a one of the nst promising digital modulation techniques adapted for Digital audio broadcasting or Digital TV since it is very robust against multipath fading channels. From 1997, since the OFDM technique was considered as the physical layer standard for the high data rate wireless LAN systems in the 5㎓ band, related studies have been studied actively. The key element to implement high data rate wireless LAN system using OFDM technique are IFFT and FFT modules. In this paper, new IFFT and FFT module are designed and implemented using current cut circuit based on the matrix-rounding process for the low-power consumptive operation and high-speed data processing. In addition to, we certify the available operation of the rounded IFFT/FFT module in the AWGN channel by using the BER performance simulation of IEEE 802.11TGa based OFDM modem with rounded IFFT/FFT module.

Performance Improvement of Current Memory for Low Power Wireless Communication MODEM (저전력 무선통신 모뎀 구현용 전류기억소자 성능개선)

  • Kim, Seong-Kweon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.3 no.2
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    • pp.79-85
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    • 2008
  • It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

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Corrosive control of the water produced by SWRO and Application to small dimensional Pilot Plant (SWRO 생산수의 부식성 제어를 위한 목표 수질 연구 및 소규모 Pilot Plant 적용)

  • Kim, Min-Chul;Hwang, Kyu-Won;Woo, Dal-Sik;Yoon, Seok-Min;Moon, Jung-Gi;Kwak, Moung-Hwa
    • Proceedings of the KAIS Fall Conference
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    • 2009.12a
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    • pp.1042-1045
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    • 2009
  • 역삼투식 해수담수화 (Sea Water Reverse Osmosis, SWRO) 공정에 의한 생산수는 pH가 낮고, 해수 내 존재하는 경도성분인 Ca, Mg 이온이 대부분 제거되기 때문에 상대적으로 매우 강한 부식성을 지니고 있다. 이를 음용수 및 공업용수로 이용 시 설비 및 배관계통에 심각한 부식문제를 유발할 수 있으며, 이를 방지하기 위한 처리공정과 부식성 제어 기술의 지속적인 개발이 요구되는 실정이다. SWRO 1단으로 처리 시 생산수의 전기전도도는 $150{\mu}S/cm$ 정도의 범위를 보이며, 2단 SWRO 과정을 거칠 시 전기전도도는 $100{\mu}S/cm$ 이하의 범위를 나타내는 것으로 알려져 있다. 본 연구에서는 SWRO 2단 처리수를 가정한 $20{\mu}S/cm{\sim}25{\mu}S/cm$ 범위의 전기전도도를 지닌 물을 실험 원수로 사용하여, 기존 방식제의 성분과 생산수의 특성을 고려한 효율적인 알칼리성 수처리제를 적용하고 그에 대한 부식성 제어 연구를 수행하였다. SWRO 생산수를 대상으로 부식방지기술을 개발하기 위해서는 부식제어와 관련된 수질 인자인 pH, 칼슘경도, 알칼리도의 조절과 LSI(Langelier Saturation Index)를 설정하는 것이 무엇보다도 중요하다. 본 연구에서는 해수담수화 공정의 생산수를 음용수 및 공업용수로 이용하기 위한 목표 수질을 pH 7.5~7.8, LSI 0 이상, 부가적으로 전기전도도는 $250{\mu}S/cm$ 이하로 설정하였으며, 연구목표 수질을 달성할 수 있는 부식억제제 및 알칼리성 수처리제의 적용을 통해 목표 수질에 대한 설정 근거를 마련하고자 하였다.

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A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing

  • Kim, Jung-Tae;Kim, In-Soo;Lee, Keon-Ho;Kim, Yong-Hyun;Baek, Chul-Ki;Lee, Kyu-Taek;Min, Hyoung-Bok
    • Journal of Electrical Engineering and Technology
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    • v.4 no.4
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    • pp.559-565
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    • 2009
  • Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

Comparison and Analysis of Subject Classification for Domestic Research Data (국내 학술논문 주제 분류 알고리즘 비교 및 분석)

  • Choi, Wonjun;Sul, Jaewook;Jeong, Heeseok;Yoon, Hwamook
    • The Journal of the Korea Contents Association
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    • v.18 no.8
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    • pp.178-186
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    • 2018
  • Subject classification of thesis units is essential to serve scholarly information deliverables. However, to date, there is a journal-based topic classification, and there are not many article-level subject classification services. In the case of academic papers among domestic works, subject classification can be a more important information because it can cover a larger area of service and can provide service by setting a range. However, the problem of classifying themes by field requires the hands of experts in various fields, and various methods of verification are needed to increase accuracy. In this paper, we try to classify topics using the unsupervised learning algorithm to find the correct answer in the unknown state and compare the results of the subject classification algorithms using the coherence and perplexity. The unsupervised learning algorithms are a well-known Hierarchical Dirichlet Process (HDP), Latent Dirichlet Allocation (LDA) and Latent Semantic Indexing (LSI) algorithm.

Low Power Current mode Signal Processing for Maritime data Communication (해상 데이터 통신을 위한 저전력 전류모드 신호처리)

  • Kim, Seong-Kweon;Cho, Seung-Il;Cho, Ju-Phil;Yang, Chung-Mo;Cha, Jae-sang
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.8 no.4
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    • pp.89-95
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    • 2008
  • In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

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The Study on Development of Plating Technique on Electroless Ni/Au (무전해 니켈/금도금 기술 개발에 관한 연구)

  • Park Soo-Gil;Park Jong-Eun;Jung Seung-Jun;Yum Jae-Suk;Jun Sae-ho;Lee Ju-Seong
    • Journal of the Korean Electrochemical Society
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    • v.2 no.3
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    • pp.138-143
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    • 1999
  • Recently, miniaturization of large scale integrated circuits (LSI) and printed circuit board (PCB) have become essential with the downsizing of electronic devices. Gold electroplating is applied of conductivity wiring or terminals for improvement of conductivity and corrosion resistance. However, electroplating is not applicable since the circuits are becoming finer and denser. Accordingly, electroless plating is recently highly attractive method because of the simplicity of the operation requiring no external source of current and no elaborate equipment. In this work, we tried to develop a plating technique on electroless Ni/Au plating. First, the electroless Ni plating was deposited on the PCB with agitation in the bath at $85^{\circ}C$. Then the Au layer was deposited on the Ni layer surface by same method at $90^{\circ}C$. The bonderability were tested in order to evaluate the stability of the electroless Ni/Au by gold wire or solder ball test.

A Loop Filter Size and Spur Reduced PLL with Two-Input Voltage Controlled Oscillator (두 개의 입력을 가진 VCO를 이용하여 루프필터와 스퍼 크기를 줄인 위상고정루프)

  • Choi, Young-Shig;Moon, Dae-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.8
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    • pp.1068-1075
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    • 2018
  • In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.