• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Bulletin of the Korean Chemical Society
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• v.34 no.2
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• pp.475-481
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• 2013

By using ionic liquid 1-hexylpyridinium hexafluorophosphate ($HPPF_6$) based carbon ionic liquid electrode (CILE) as the substrate electrode, a $CoMoO_4$ nanorods and myoglobin (Mb) composite was casted on the surface of CILE with chitosan (CTS) as the film forming material to obtain the modified electrode (CTS/$CoMoO_4$-Mb/CILE). Spectroscopic results indicated that Mb retained its native structures without any conformational changes after mixed with $CoMoO_4$ nanorods and CTS. Electrochemical behaviors of Mb on the electrode were carefully investigated by cyclic voltammetry with a pair of well-defined redox peaks from the heme Fe(III)/Fe(II) redox center of Mb appeared, which indicated that direct electron transfer between Mb and CILE was realized. Electrochemical parameters such as the electron transfer number (n), charge transfer coefficient (${\alpha}$) and electron transfer rate constant ($k_s$) were estimated by cyclic voltammetry with the results as 1.09, 0.53 and 1.16 $s^{-1}$, respectively. The Mb modified electrode showed good electrocatalytic ability toward the reduction of trichloroacetic acid in the concentration range from 0.1 to 32.0 mmol $L^{-1}$ with the detection limit as 0.036 mmol $L^{-1}$ ($3{\sigma}$), and the reduction of $H_2O_2$ in the concentration range from 0.12 to 397.0 ${\mu}mol\;L^{-1}$ with the detection limit as 0.0426 ${\mu}mol\;L^{-1}$ ($3{\sigma}$).