• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.11C
• /
• pp.901-906
• /
• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.639-642
• /
• 2005

This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.473-476
• /
• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• Journal of Broadcast Engineering
• /
• v.16 no.4
• /
• pp.635-646
• /
• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.12
• /
• pp.2783-2790
• /
• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.8C
• /
• pp.522-528
• /
• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.4
• /
• pp.160-172
• /
• 2014

Although Wyner-Ziv (WZ) video coding proves useful for applications employing encoders having restricted computing resources, the WZ decoder has a problem of excessive decoding complexity. It is mainly due to its iterative LDPC channel decoding process which repeatedly requests incremental parity data after iterative channel decoding of parity data received at each request. In order to solve the complexity problem, we divide bit planes into two groups and estimate the minimum required number of parity requests separately for the two groups of bit planes using bit plane correlation. The WZ decoder executes the iterative decoding process only after receiving parity data corresponding to the estimated minimum number of parity requests. The proposed method saves about 71% of the computing time in the LDPC decoding process.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.7C
• /
• pp.587-593
• /
• 2010

In this paper we design an irregular low-density parity-check (LDPC) code for multiple-input multiple-output (MIMO) system, using a simple extrinsic information transfer (EXIT) chart method. The MIMO systems considered are optimal maximum a posteriori probability (MAP) detector. The MIMO detector and the LDPC decoder exchange soft information and form a turbo iterative receiver. The EXIT charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the MIMO detector. It is shown that the performance of the designed LDPC code is better than that of conventional LDPC code which was optimized for either the Additive White Gaussian Noise (AWGN) channel or the MIMO channel.

• ETRI Journal
• /
• v.30 no.6
• /
• pp.807-817
• /
• 2008

We present a low-density parity-check (LDPC)-based, threaded layered space-time-frequency system with emphasis on the iterative receiver design. First, the unbiased minimum mean-squared-error iterative-tree-search (U-MMSE-ITS) detector, which is known to be one of the most efficient multi-input multi-output (MIMO) detectors available, is improved by augmentation of the partial-length paths and by the addition of one-bit complement sequences. Compared with the U-MMSE-ITS detector, the improved detector provides better detection performance with lower complexity. Furthermore, the improved detector is robust to arbitrary MIMO channels and to any antenna configurations. Second, based on the structure of the iterative receiver, we present a low-complexity belief-propagation (BP) decoding algorithm for LDPC-codes. This BP decoder not only has low computing complexity but also converges very fast (5 iterations is sufficient). With the efficient receiver employing the improved detector and the low-complexity BP decoder, the proposed system is a promising solution to high-data-rate transmission over selective-fading channels.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1872-1873
• /
• 2007

최근 유럽에서는 사용자와 운영자들의 요구에 부응하여 기존 DVB 위성 광대역 서비스에 대한 표준을 DVB-S에서 DVB-S2로 업그레이드 시켰다. DVB-S2는 ACM을 적용하여 여러 채널환경에서 기존의 표준보다 안정적인 전송과 높은 효율을 보여준다. DVB-S2 시스템은 FEC 알고리듬으로써 LDPC와 BCH를 사용하고 있다. LDPC는 R. G. Gallager에 의해 고안된 블록부호화 방식으로 검사행렬 H에서 1의 sparse 한 성질을 이용하여 큰 블록에서 더 좋은 성능을 발휘하도록 되어있다. 본 논문에서는 DVB-S2의 중요 서브시스템인 FEC블록 중 LDPC 복호기에 관하여 ACM을 적용하여 상위수준 시뮬레이션을 실시하였다. 실험결과 각 변조 방식 및 부호율에 따라서 BER이 SNR 0에서 14dB까지 넓게 분포함을 확인하였다. 그러므로 채널 환경에 따라 변조방식과 부호율을 달리하여 속도를 향상시키거나 데이터의 안정성을 높일 수 있다. 그리고 이 때 LDPC 복호기가 충분히 성능을 발휘함을 알 수 있다.