• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Journal of IKEEE
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• v.25 no.1
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• pp.201-205
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• 2021

In this paper present Low Drop-Out (LDO) regulator that improved load transient characteristics due to the push-pull detection structure. The response characteristic of the voltage delta value is improved due to the proposed push-pull sensing circuit structure between the input terminal of the LDO regulator pass transistor and the output terminal of the internal error amplifier. Voltage value has improved load transient characteristics than conventional LDO regulator. Compared to the conventional LDO regulator, it has an improved response speed of approximately 244 ns at rising time and approximately 90 ns at falling time. The proposed circuit was simulated by the samsung 0.13um process using Cadence's Specter and Virtuoso simulator.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2729-2734
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• 2011

In this paper, an active replica Low-dropout(LDO) regulator with DC voltage matching circuit is presented. In order to match the voltage between replica and output of regulator, DC voltage matching circuit is designed. The active replica low dropout regulator has higher Power Supply Rejection(PSR) than that of conventional regulator. The designed DC voltage matching circuit can reduce the drawback that may be occurred in replica regulator. And using fully active element in regulator can reduce the chip area and heat noise with resistor. As results of HSPICE simulation with 0.35um CMOS parameter, the designed active replica LDO regulator achieves Power Supply Rejection, -28@10Hz better than -17@10Hz of conventional replica regulator without DC matching circuit. And the output voltage is 3V.

• Journal of IKEEE
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• v.17 no.2
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• pp.214-220
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• 2013

Small area LDO (Low drop-out) regulator with pass transistor using body-driven technique is presented in this paper. The body-driven technique can decrease threshold voltage (Vth) and increase the current ID flowing from drain to source in current. The technique is applied to the pass transistor to reduce size of area and maintain the same performance as conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5 %. The proposed LDO regulator works under the input voltage of 2.7 V ~ 4.5 V and provides up to 150mA load current for an output voltage range of 1.2 V ~ 3.3 V.

• Journal of IKEEE
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• v.25 no.3
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• pp.506-510
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• 2021

In this paper, we propose an LDO that improves the load regulation change due to the current detection structure. The proposed LDO regulator adds the proposed current detection circuit to the output stage. Thereby to improve the load regulation of the delta value coming in on the output has a voltage value of an improved load Regulation characteristics than conventional LDO regulator. Using the proposed current detection structure, it was possible to improve the output change according to the change of the load current by about 60%. The proposed circuit has been simulated and verified characteristics by using a Spectre, Virtuoso simulation of Cadence.

• Journal of IKEEE
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• v.26 no.1
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• pp.124-128
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• 2022

Conventional LDO regulator external capacitors can reduce transient response characteristics such as overshoot and undershoot. However, the capacitorless LDO regulator proposed in this study applied body technology to the pass transistor to improve the transient response and provide excellent current drive capability. The operating conditions of the proposed LDO regulator are set to an input voltage that varies from 3.3V to 4.5V, a maximum load current of 200mA, and an output voltage of 3V. As a result of the measurement, it was found that when the load current was 100 mA, the voltage was 95 mV in the undershoot state and 105 mV in the overshoot state.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

• Journal of IKEEE
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• v.24 no.2
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• pp.598-603
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• 2020

In this paper present a Low Drop-Out(LDO) regulator that improves load transient characteristics due to the push-pull pass transistor structure is proposed. Improved load over the existing LDO regulator by improving the overshoot and undershoot entering the voltage line by adding the proposed push-pull circuit between the output stage of the error amplifier inside the LDO regulator and the gate stage of the pass transistor and the push-pull circuit at the output stage. It has a delta voltage value of transient characteristics. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• Journal of IKEEE
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• v.27 no.3
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• pp.308-312
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• 2023

The gate current sensing structure was proposed to more effectively control the regulation of the output voltage when the LDO regulator occurs in an overshoot or undershoot situation. In a typical existing LDO regulator, the regulation voltage changes when the load current changes. However, the operation speed of the pass transistor can be further improved by supplying/discharging the gate terminal current in the pass transistor using a gate current sensing structure. The input voltage of the LDO regulator using the gate current sensing structure is 3.3 V to 4.5 V, the output voltage is 3 V, and the load current has a maximum value of 250 mA. As a result of the simulation, a voltage change value of about 12 mV was confirmed when the load current changed up to 250 mA.

• Journal of IKEEE
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• v.19 no.3
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• pp.304-310
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• 2015

A SCALDO(Supercapacitor Assisted LDO) regulator is a new regulator having advantages of a SMPS(Switch Mode Power Supply) which has a good efficiency and a LDO(Low Drop-out) regulator which has stable output characteristics and good EMI(Electro Magnetic Interference) characteristics. However, a conventional SCALDO regulator needs a lot of power consumption to control its switches and it drops an efficiency of the circuit. In this paper, to reduce switching power consumption and improve an efficiency of the circuit, a new SCALDO regulator adopting MOSFETs as its switching parts is proposed and it is found out that the proposed SCALDO regulator has the maximum 9.5% higher efficiency than the conventional SCALDO regulator. We also try to simplify production process of the circuit by changing switching control method of the circuit from MCU(Micro-controller unit) based firmware control to hardware control using a comparator and a T-F/F(Flip Flop).