• Title/Summary/Keyword: LDD

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Hot-Carrier Effects of $BF_2$ Ion-Implanted Surface-Channel LDD PMOSFET ($BF_2$ 이온 주입한 표면 채널 LDD PMOSFET의 Hot-Carrier 효과)

  • 양광선;박훈수;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.12
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    • pp.53-58
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    • 1991
  • Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

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A Method for Effective Channel Length Extraction on Lightly Doped Drain MOSFET's (LDD MOSFET의 유효 채널길이 측정법에 관한 연구)

  • Park, Geun-Young;Huh, Yoon-Jong;Lee, Kye-Shin;Sung, Yung-Kwon
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.825-828
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    • 1992
  • In this paper, a Hybrid method for an effective channel length($L_{eff}$) on lightly doped drain(LDD) MOSFET's is proposed. In order to investigate the difference of the gate bias and substrate bias defendence of the $L_{eff}$ among various LDD structures, the $L_{eff}$ of the LDD's are extensively examined using simulations and measurement. one group is proposed for conventional MOSFET and the other group Is proposed for LDD MOSFET. It is shown that the $V_{bs}$-dependence of the n-region is different from $V_{gs}$-dependence of it.

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The Extraction Method of LDD NMOSFET's Metallurgical Gate Channel Length (LDD NMOSFET의 Metallurgical 게이트 채널길이 추출 방법)

  • Jo, Myung-Suk
    • Journal of IKEEE
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    • v.3 no.1 s.4
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    • pp.118-125
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    • 1999
  • A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

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Effect of Dopants on Cobalt Silicidation Behavior at Metal-oxide-semiconductor Field-effect Transistor Sidewall Spacer Edge

  • Kim, Jong-Chae;Kim, Yeong-Cheol;Kim, Byung-Kook
    • Journal of the Korean Ceramic Society
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    • v.38 no.10
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    • pp.871-875
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    • 2001
  • Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

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Long-term evaluations of teeth and dental implants during dental maintenance period

  • Yoon, Da-Le;Kim, Yong-Gun;Cho, Jin-Hyun;Lee, Jae-Mok;Lee, Sang-Kyu
    • The Journal of Advanced Prosthodontics
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    • v.9 no.3
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    • pp.224-231
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    • 2017
  • PURPOSE. This study was designed to evaluate the teeth and dental implants during dental maintenance therapy over 3 years in different conditions after periodontal and dental prosthetic treatment. MATERIALS AND METHODS. 166 patients received maintenance therapy. 59 patients were treated with 2% minocycline-HCl ointment as local drug delivery (LDD) (L group) and 107 patients were treated without LDD (NL group). Clinical data was collected in maintenance period for evaluation. Patients were classified into groups depending on the application of LDD with maintenance therapy, the type of dental treatment before maintenance period (Pre-Tx), the frequency (F-MT), and regularity (R-MT) of maintenance therapy. RESULTS. The numbers of lost teeth (N-teeth, P=.003) and newly placed dental implants (N-implants, P=.022) are significantly different according to Pre-Tx. F-MT among patients who received surgical dental treatment before maintenance period showed statistical differences in N-teeth (P=.041), but not in N-implants (P=.564). All of the patients in L group showed high F-MT (F-MT1). In NL group, there were no statistical differences in N-teeth or N-implants according to F-MT or R-MT. In F-MT1 group, application of LDD made N-teeth significantly different from both Pre-Tx groups while no significant difference could be found in N-implant. Independent t-test and one-way ANOVA were selected for statistical analysis. CONCLUSION. The regular maintenance therapy and LDD can be effective for teeth during maintenance period. It is not only pharmacological efficacy in decreasing bacterial species that makes LDD a useful adjunct. Application of LDD also motivates patients to take adequate check-ups in the aspects of both frequency and regularity.

A Study on Punchthrough and Hot-carrier Effects as LDD Process Parameters (LDD 공정 조건에 따른 편치쓰루 및 핫 캐리어 효과에 관한 연구)

  • An, Tae-Hyun;Kim, Nam-Hoon;Kim, Chang-Il;Seo, Yong-Jin;Chang, Eui-Goo
    • Proceedings of the KIEE Conference
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    • 1998.07d
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    • pp.1367-1369
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    • 1998
  • To achieve the ULSI goals of higher density, greater performance and operation speed have been scaled down. However, the reduction of channel length cause undesirable problems such as drop of punchthrough voltage, hot-carrier degradation and high leakage current, etc.. It is shown that the device characteristics depend on process parameters. In this Paper, we catched hold of trends of hot-carrier effects and punchthrough voltages due to variation of some process parameters such as LDD doses(P), spacer lengths, channel doses($BF_2$) and $V_T$ adjusting channel implantation energies using design trend curve (DTC). As the LDD and channel doses increased, hot-carrier phenomena became more severe, and punchthrough voltage was decreased. It were represented that punchthrough and hot carrier effects were critically depend on LDD and channel doses.

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An Experimental Investigation of LDD Device Optimization (LCD 소자 최적화의 실험적 고찰)

  • Kang, Dae-Gwan;Kim, Dal-Soo;Kim, Hyun-Chul;Song, Nag-Un
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.3
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    • pp.72-78
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    • 1990
  • In this paper, the physical meanings of LDD optimization are treated by numerical simulation and related experiments are attempted to analyzed the optimized LDD structure. Firstly, according to the numerical analysis, the electric field under the n-region near drain is low and uniformly distributed and the current flow is widely distributed in this region under the optimized conditions. It is also found that this optimized point should be achieved by globally optimizing all the process and electrical conditions. Secondly, the maximum electric field, which is obtained from the substrate current to the drain current ratio, is minimized under the optimized condition according to the experiment. Further, the device lifetime is maximized and the n-resistance is changed smoothly from the channel resistance to the $n^+$junction resistance.

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Design of the 25nm LDD MOSFET Process using MicroTec Tool (MicroTec을 이용한 25nm LDD MOSFET Process 설계)

  • Han, Ji-Hyung;Jung, Hak-Kee;Lee, Jae-Hyung;Jeong, Dong-Soo;Lee, Jong-In;Kwon, Oh-Shin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.588-591
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    • 2008
  • 본 연구에서는 MicroTec을 이용하여 25nm LDD MOSFET Process를 구현하였다. LDD MOSFET의 저농도 도핑은 드레인의 끝에서 발생할 수 있는 핫 캐리어 효과를 감소시키는데 도움을 주며, 낮은 접합깊이는 DIBL 효과 및 전하공유와 같은 단채널효과를 감소시키는 중요한 역할을 한다. MicroTec 툴의 Sidif를 사용하여 25nm LDD MOSFET process를 설계하였고, 시뮬레이션 하는 과정과 방법을 설명하였다. 이온주입 양과 에너지의 크기를 증가하면서 전체도핑농도를 비교 분석하였다. 이온주입 양을 증가시키고 에너지의 크기가 커지면 더 강한 에너지가 가해지게되므로 높게 도핑되는 영역이 확장되고 전체 농도분포도 역시 확장되는걸 알 수 있었다.

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Study on the Vibration Characteristics of Yaw Gear System for Large-Capacity Offshore Wind Turbine

  • HyoungWoo Lee;SeoWon Jang;Seok-Hwan Ahn
    • Journal of Ocean Engineering and Technology
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    • v.37 no.4
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    • pp.164-171
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    • 2023
  • Vibration and noise must be considered to maximize the efficiency of a yaw system and reduce the fatigue load acting on a wind turbine. This study investigated a method for analyzing yaw-system vibration based on the change in the load-duration distribution (LDD). A substructure synthesis method was combined with a planetary gear train rotational vibration model and finite element models of the housing and carriers. For the vibration excitation sources, the mass imbalance, gear mesh frequency, and bearing defect frequency were considered, and a critical speed analysis was performed. The analysis results showed that the critical speed did not occur within the operating speed range, but a defect occurred in the bearing of the first-stage planetary gear system. It was found that the bearing stiffness and first natural frequency increased with the LDD load. In addition, no vibration occurred in the operating speed range under any of the LDD loads. Because the rolling bearing stiffness changed with the LDD, it was necessary to consider the LDD when analyzing the wind turbine vibration.

A study hot-carrier degradation on submicron devices (Submicron device에서의 hot-carrier 열화에 관한 연구)

  • 이용희;김현호;최영규;이천희
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.867-870
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    • 1998
  • In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

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