• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.42-49
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• 2007

This paper introduces a study on reliability-driven device placement using simulated annealing algorithm which can be applicable to MCM or electronic systems embedded in a spacecraft running at thermal conduction environment. Reliability of the unit's has been predicted with the devices' junction temperatures calculated from FDM solver and optimized by simulated annealing algorithm. Simulated annealing in this paper adopts swapping devices method as a perturbation. This paper describes and compares the optimization simulation results with respect to two objective functions: minimization of failure rate and minimization of average junction temperature. Annealing temperature variation simulation case and equilibrium coefficient variation simulation case are also presented at the two respective objective functions. This paper proposes a new approach for reliability optimization of MCM and electronic systems considering those simulation results.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.816-823
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• 2016

This paper studies a light emitting diode(LED) overlapping method of a head-up display that consists of a digital micro device(DMD) panel and a red, green, blue LED in order to increase the brightness of display system and optical output power. This optimization overlapping method removes a quantization noise which occur due to LED overlapping too excessive and stabilizes the junction temperature of LED. In order to reduce junction temperature of LED, the a correlation between a green duty and LED overlapping ratio is studied. Throughout this study, the brightness of head-up display exhibited high increasement ratio of luminance around 33.3 percent at 39 percent overlapping method.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.315.1-315.1
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• 2014

The use of cellulose papers has recently attracted much attention in various device applications owing to their natural advantageous properties of earth's abundance, bio-friendly, large-scale production, and flexibility. Conventional metal oxides with novel structures of nanorods, nanospindles, nanowires and nanobelts are being developed for emerging electronic and chemical sensing applications. In this work, both ZnO (n-type) nanorod arrays (NRAs) and CuO (p-type) nanospindles (NSs) were synthesized on cellulose papers and the p-n junction property was investigated using the electrode of indium tin oxide coated polyethylene terephthalate film. To synthesize ZnO and CuO nanostructures on cellulose paper, a simple and facile hydrothermal method was utilized. First, the CuO NSs were synthesized on cellulose paper by a simple soaking process, yielding the well adhered CuO NSs on cellulose paper. After that, the ZnO NRAs were grown on CuO NSs/cellulose paper via a facile hydrothermal route. The as-grown ZnO/CuO NSs on cellulose paper exhibited good crystalline and optical properties. The fabricated p-n junction device showed the I-V characteristics with a rectifying behaviour.

• Journal of Power Electronics
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• v.13 no.6
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• pp.1080-1089
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• 2013

In this paper, the superposition principle of a heat sink temperature rise is verified based on the mathematical model of a plate-fin heat sink with two mounted heat sources. According to this, the distributed coupling thermal impedance matrix for a heat sink with multiple devices is present, and the equations for calculating the device transient junction temperatures are given. Then methods to extract the heat sink thermal impedance matrix and to measure the Epoxy Molding Compound (EMC) surface temperature of the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) instead of the junction temperature or device case temperature are proposed. The new thermal impedance model for the power converters in Switched Reluctance Motor (SRM) drivers is implemented in MATLAB/Simulink. The obtained simulation results are validated with experimental results. Compared with the Finite Element Method (FEM) thermal model and the traditional thermal impedance model, the proposed thermal model can provide a high simulation speed with a high accuracy. Finally, the temperature rise distributions of a power converter with two control strategies, the maximum junction temperature rise, the transient temperature rise characteristics, and the thermal coupling effect are discussed.

• Journal of IKEEE
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• v.25 no.2
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• pp.356-361
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• 2021

Super Junction structure is the proposed structure to minimize the Trade-off phenomenon of power devices. Super Junction can have On-resistance(Ron) characteristics as less as five times than conventional structure. There are process methods that Multi-Epi and Deep-Trench of Super Junction structure. The reason for this is that Deep-Trench process is known to be a relatively difficult manufacturing method because it is easy to form a P-Pillar by burying impurities on top of a silicon substrate through a Deep-Trench process. However, the structure created by the Deep-Trench process has low On-resistance and high breakdown voltage, showing better efficiency. In this paper, we suggested a novel method in the process and designed structure with Charge Balance theory.

• Journal of the Korean Vacuum Society
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• v.19 no.5
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• pp.391-396
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• 2010

The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor to research the characteristic of interface at pn junction. The sheet resistance was decreased in accordance with the increasing the diffusion process time for n-type doping on p-type Si wafer. The electron affinity at the interface in the pn junction was decreased with increasing the amount of n-type doping and the sheet resistance also decreased. Consequently, the drift current due to the generation of EHP increased because of low potential barrier. The efficiency and fill factor were increased at the solar cell with increasing the diffusion process time.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.17-20
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• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.