• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.389.2-389.2
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• 2016

The flexible solid state device has been widely studied as portable and wearable device applications such as display, sensor and curved circuits. A zero-bias operation without any external power consumption is a highly-demanding feature of semiconductor devices, including optical communication, environment monitoring and digital imaging applications. Moreover, the flexibility of device would give the degree of freedom of transparent electronics. Functional and transparent abrupt p/n junction device has been realized by combining of p-type NiO and n-type ZnO metal oxide semiconductors. The use of a plastic polyethylene terephthalate (PET) film substrate spontaneously allows the flexible feature of the devices. The functional design of p-NiO/n-ZnO metal oxide device provides a high rectifying ratio of 189 to ensure the quality junction quality. This all transparent metal oxide device can be operated without external power supply. The flexible p-NiO/n-ZnO device exhibit substantial photodetection performances of quick response time of $68{\mu}s$. We may suggest an efficient design scheme of flexible and functional metal oxide-based transparent electronics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.286-289
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• 1991

We simulated ion implantation and annealing condition of 1 ${\mu}m$ CMOS device using process simulator, SUPREM-II. In this simulation, optimal condition of ion implantation for symmetric threshold voltage determination of PMOS and NMOS region, junction depth and sheet resistance of source/drain region, impurity profile of each region are investigated. Ion implantation dose for 3 ${\mu}m$ N-well junction depth and symmetric threshold voltage of $|0.6|{\pm}0.1$ V were $1.9E12Cm^{-2}$(for phosphorus), $1.7E122Cm^{-2}$(for boron) respectively. Also annealing condition for dopant activation are examined about $900^{\circ}C$, 30 minutes. After final process step, N-well junction, P+ S/D junction and N+ S/D junction depth are calculated 3.16 ${\mu}m$, 0.45 ${\mu}m$ and 0.25 ${\mu}m$ respectively.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권6호
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• pp.257-260
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• 2003

We have proposed the junction termination structure of IGBT (Insulated Gate Bipolar Transistor) by employing trench and FLR (Field Limiting Ring), which decrease the junction termination area at the same breakdown voltage. Our proposed junction termination structure, trench FLR is verified by numerical simulator MEDICI. In 600V rated device, the junction termination area is decreased 20% compared with that of the conventional FLR structure. The breakdown voltage of trench FLR with 4 trenches is 768 V, 99 % of ideal parallel-plane junction(1-D) $BV_ceo$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.70-81
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• 2002

This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.

• Applied Microscopy
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• 제50권
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• pp.17.1-17.9
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• 2020

Recent advances in fabrication have enabled radial-junction architectures for cost-effective and high-performance optoelectronic devices. Unlike a planar PN junction, a radial-junction geometry maximizes the optical interaction in the three-dimensional (3D) structures, while effectively extracting the generated carriers via the conformal PN junction. In this paper, we report characterizations of radial PN junctions that consist of p-type Si micropillars created by deep reactive-ion etching (DRIE) and an n-type layer formed by phosphorus gas diffusion. We use electron-beam induced current (EBIC) microscopy to access the 3D junction profile from the sidewall of the pillars. Our EBIC images reveal uniform PN junctions conformally constructed on the 3D pillar array. Based on Monte-Carlo simulations and EBIC modeling, we estimate local carrier separation/collection efficiency that reflects the quality of the PN junction. We find the EBIC efficiency of the pillar array increases with the incident electron beam energy, consistent with the EBIC behaviors observed in a high-quality planar PN junction. The magnitude of the EBIC efficiency of our pillar array is about 70% at 10 kV, slightly lower than that of the planar device (≈ 81%). We suggest that this reduction could be attributed to the unpassivated pillar surface and the unintended recombination centers in the pillar cores introduced during the DRIE processes. Our results support that the depth-dependent EBIC approach is ideally suitable for evaluating PN junctions formed on micro/nanostructured semiconductors with various geometry.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.458-464
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• 2017

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

• ETRI Journal
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• 제34권1호
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• pp.134-137
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• 2012

Power metal-oxide semiconductor field-effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double-diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. To overcome the tradeoff relationship, a super-junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-state resistance of 1.2 $m{\Omega}-cm^2$ at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.

• Journal of Information Display
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• 제13권1호
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• pp.1-6
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• 2012

Decreasing the thermal resistance is the critical issue for high-brightness light-emitting diodes. In this paper, the effects of some design factors, such as chip size (24 and 35 mil), substrate material (AlN and high-temperature co-fired ceramic), and die-attach material (Ag epoxy and PbSn solder), on the thermal-dissipation characteristics were investigated. Using the thermal transient method, the temperature sensitivity parameter, $R_{th}$ (thermal resistance), and junction temperature were estimated. The 35-mil chip showed better thermal dissipation, leading to lower thermal resistance and lower junction temperature, owing to its smaller heat source density compared with that of the 24-mil chip. By adopting an AlN substrate and a PbSn solder, which have higher thermal conductivity, the thermal resistance of the 24-mil chip can be decreased and can be made the same as that of the 35-mil chip.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.