• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2658-2663
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• 2008

In the present study, we designed a microfluidic flatform that generates monodisperse droplets with diameters ranging from hundreds of nanometers to several micrometers. To generate fine droplets, T-junction and flow-focusing geometry are integrated into the microfluidic channel. Relatively large aqueous droplets are generated at the upstream T-junction and transported toward the flow-focusing geometry, where each droplet is broken up into the targeted size by the action of viscous stresses. Because the droplet prior to rupture blocks the straight channel that leads to the flow-focusing geometry, it moves very slowly by the pressure difference applied between the advancing and receding regions of the moving droplet. This configuration enables very low flow rate of inner fluid and higher flow rate ratio between inner and outer fluids at the flow-focusing region. It is shown that the present microfluidic device can generate droplets with diameters about 1 micrometer size and standard deviation less than 3%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Progress in Superconductivity
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• 제3권1호
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• pp.41-44
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• 2001

We report the current transport properties of a normal metal/organic conductor/ superconductor tunnel junction as a novel high- $T_{c}$ superconducting three terminal device. The organic copper (II) phthalocyanine (Cu-Pc) layer was used far a polaronic quasiparticle (QP) injector. The injection of polaronic QP from the Cu-Pc interlayer into a superconductor $Bi_2$$Sr_2$$CaCu_2$ $O_{8+}$ $\delta$/(BSCCO) thin film generated a substantially larger nonequilibrium effect as compared to the normal QP injection current. The tunneling spectroscopy of an Au/cu-PC/BSCCO junction exhibited a zero bias conductance peak which may be due to Andreev reflection at a Cu-Pc/d-wave superconductor junction.n..

• 공업화학
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• 제9권5호
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• pp.710-714
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• 1998

Poly(p-phenylene vinylene), PPV를 발광층으로 하고 전자수송층(electron transport layer, ETL)이 도입된 이중 접합구조 유기 전기발광소자(electroluminescence device, ELD)를 제작하고 전기 발광 특성을 조사하였다. 전자 수송제로는 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole(PBD)를 사용하고 이를 분산시킬 기재 고분자(matrix polymer)로는 stilbene계 공단량체를 포함하는 poly(styrene-co-p-vinyl-trans-stilbene (PVTS)), poly(styrene-co-MeO-PVTS) 및 poly(styrene-co-MeO-ST)를 합성하였다. 이들 재료를 이용하여 이종 접합구조 ELD를 제조하였으며 poly(styrene-co-PVTS)를 기재 고분자로 쓴 EL 소자가 최대의 휘도를 나타냄을 확인하였다. Poly(styrene-co-MeO-PVTS) 및 poly(styrene-co-MeO-ST) 등 전자 주게 성질을 가진 methoxy기를 함유하는 기재 고분자를 쓴 EL 소자는 전자 수송층이 없는 ITO/PPV/Mg 단층 소자와 휘도가 유사 혹은 낮게 나타났다. Poly(styrene-co-PVTS)를 ETL에 쓴 EL 소자에 있어서 styrene보다 긴 conjugation 길이의 증가가 EL 발광 스펙트럼에 미치는 영향은 크지 않고 실제 발광은 PPV에 의해 주로 일어남이 관찰되었다.

• 전기전자학회논문지
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• 제7권1호
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• pp.1-8
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• 2003

본 논문에서는 고내압 및 고속 스위칭 특성을 갖는 고성능 BCD(Bipolar- CMOS-DMOS) 소자 구조를 고안하였다. 공정 및 소자 시뮬레이션을 통하여, 최적화된 공정 규격과 소자 규격을 설계하였으며, 고안된 소자의 전기적 특성을 만족시키기 위하여 이중 매몰층 구조, 트랜치 격리 공정, n-/p- 드리프트 영역 형성기술 및 얕은 접합 깊이 형성기술 등을 채택하였다. 이 스마트 파워 IC는 20V급 Bipolar npn/pnp 소자, 60V급 LDMOS소자, 수 암페어급의 VDMOS, 20V급 CMOS소자 그리고 5V급 논리 CMOS를 내장하고 있다.

• 한국산학기술학회논문지
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• 제18권6호
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• pp.37-43
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• 2017

본 논문에서는 고출력 전자기파 (Electromagnetic pulses, EMP) 영향에 의해 발생하는 반도체 부품의 물리적 상호작용에 대한 원리와 고장 발생 메커니즘의 연구를 위해 선행된 연구 내용을 고찰하였다. 반도체 부품에서의 전자기파 전이 과정은 3층 (공기/유전체/도체) 구조로 설명할 수 있으며, 복소반사계수에 의하여 이론적으로 흡수되는 에너지를 예상할 수 있다. 반도체 부품에 전달된 과도한 고출력 전자기파로 인한 반도체 부품의 주요 고장 원인은 전자기파 커플링에 의한 부품 소재의 줄 열에너지의 발생이다. 전기장에 의한 유전가열과 자기장에 의한 맴돌이손실에 의해 반도체 칩의 P-N 접합 파괴, 회로패턴의 burn-out과 리드 프레임과 칩을 연결하는 와이어의 손상 등이 발생한다. 즉, 반도체 부품에 전달된 전자기파는 반도체 내부 물질과 상호작용을 하며, 쌍극자분극과 이온 전도도 현상이 동시에 발생하여, 칩 내부의 P-N 접합 부분에 과도한 역전압이 형성되어 P-N 접합 파괴를 유발한다. 향후 고 신뢰성을 요구하는 전기전자시스템에 대한 EMP 내성을 향상하기 위한 반도체 부품 수준의 연구가 필요하다.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Journal of Information Display
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• 제8권2호
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• pp.20-24
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• 2007

Efficient white organic light-emitting diodes are fabricated with the blue and red electroluminescent (EL) units electrically connected in a stacked tandem structure by using a transparent doped organic p/n junction. The blue and red EL units consist of the light-emitting layer of 1,4-bis(2,2-diphenyl vinyl)benzene (DPVBi) and 4-dicyanomethylene-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[i,j] quinolizin-8-yl)vinyl]-4H-pyran) (DCM2) doped tris(8-hydroxyquinoline) aluminum $(Alq_3)$, respectively. The organic p-n junction consists of ${\alpha}-NPD$ doped with $FeCl_3$ (15 % by weight ratio) and $Alq_3$ doped with Li (10 %). The EL spectra exhibit two peaks at 448 and 606 nm, resulting in white light-emission with the Commission Internationale d'Eclairage (CIE) chromaticity coordinates of (0.36, 0.24). The tandem device shows the quantum efficiency of about 2.2 % at a luminance of 100 $cd/m^2$, higher than individual blue and red EL devices.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권3호
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.