• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.548-552
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• 1987

The constraint condition of the loop filter is persented for the convergence of the random jitter accumulation fo the 2-nd order PLL (phase-locked loop) circuit used in digital regenerative repeater. This condition is confirmed under the assumption that the number of repeater chain is 5, bandwidth is 100. 0KHz, the power spectral density of white Gaussian noise is 1.0x10**-6 [W/Hz]. Also, it is shown that if the condition is satisfied, the accumulated random jitter and the alignment jitter will have the saturation characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.26-33
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• 1994

In this paper, the performance of the trellis coded CPFSK with the coherent detection over mobile communication channels is calculated. The characteristics of channels, including phase jitter effects and fading effects, are examined and modeled. The phase jitter channel is modeled to have a nonzero mean and a gaussian distribution. The fading channel has a Rayleigh distribution in the multipath. For the optimal decoding method(MLSE), the Viterbi algorithm is used for the trellis structure of trellis coded CPFSK. The results indicate that the trellis coded CPFSK with a small moulation indes gets more sensitive, as the index gets smaller, to the phase noise under the phase jitter channel. Using the interleaving method. It gives considerable improvements in the error rate under the fading channel.

• Korean Journal of Optics and Photonics
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• v.22 no.5
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• pp.223-229
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• 2011

We present a low jitter frequency up-conversion detector based on quasi-phase matched sum frequency generation in a periodically poled $LiNbO_3$ waveguide for efficient single-photon detection at 1.5 ${\mu}m$ telecommunication wavelengths. The maximum detection efficiency and the noise count rate using the pump power of 300 mW and the pump wavelength of 974 nm are about 7% and 480 kHz, respectively. We also characterize the timing jitter of the frequency up-conversion detector by analyzing the time distribution of the detection outputs for photons generated through a picosecond pump pulsed spontaneous parametric downconversion. The minimum timing jitter was measured to be about 39.1 ps. Coincidence measurement with a narrow time window for pulsed up-conversion photons can eliminate the unwanted noise counts and maximize signal to noise ratio.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2001.05a
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• pp.189-193
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• 2001

The performance of printer can be determined by the printing speed, noise level, printing quality which includes the resolution, regularity of printed matter and etc. Among them, printing quality mostly depends on the irregularity of the line spacing and dot size. The irregular line spacing and dot size in laser beam printer are mainly from the jitter which comes from the vibration of Organic Photo Conductive(OPC) drum and the Laser Scanning Unit(LSU). Jitter due to the vibration of LSU appears as high-frequency component which occurs 100-300$\mu\textrm{m}$ interval in printed matter and the causes of it can be estimated as the vibration of polygon motor, case, reflecting mirror and etc. In this paper, vibration characteristics of the LSU under development are investigated and the strategy for improvement of the dynamic characteristics is established and its validity is demonstrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• Phonetics and Speech Sciences
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• v.5 no.3
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• pp.55-60
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• 2013

The purpose of this study was to investigate the acoustic characteristics of crying infants according to the communication intents such as hunger and pain in terms of acoustic differences in the fundamental frequency ($F_0$), jitter, shimmer, noise-to-harmonic ratio(NHR), habitual pitch, and intensity. The subjects were 20 healthy, normal infants, less than seven days old, from the city of Seoul and were born after 38 to 42 weeks(full term) of pregnancy. The sound of crying was recorded for three minutes. The crying due to pain was induced by means of the inborn metabolism error test, whereas the crying due to hunger was verified by means of the rooting reflex by waiting for the designated eating time. The results were as follows: (1) the fundamental frequency, noise-to-harmonic ratio(NHR), and intensity of the infants' crying due to pain was higher than that by hunger, showing a significant difference between the mean values. (2) the infants' crying due to hunger and that by pain did not have a significant difference in the mean jitter and shimmer values but both of them were largely outside of the normal threshold values(jitter by 1.04% and shimmer by 3.81%). This study was significant in the sense that it showed the acoustic characteristics of infants' crying from hunger and pain were very different from each other according to the communication intents in terms of the six acoustic parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.107-113
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• 2005

In this paper, we have developed the miniature ceramic PECL(positive emitter-coupled logic) VCXO of the $5{\times}7mm$ size for gratifying the requested specifications and the multilayer ceramic SMD(surface mounted device) package technology. The ceramic SMD PECL VCXO designed by the inverted Mesa type HFF is operating at the 3.3 Voltage and have the frequency range of 120MHz-180MHz. The Q factor is over 5K and it has the low jitter characteristics of 3.5 ps and low phase noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.