• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1758-1765
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• 2010

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

• Journal of the Korea Society of Computer and Information
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• v.14 no.1
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• pp.81-89
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• 2009

To support dynamic Region-of-Interest(ROI) in JPEG2000, a fast ROI mask generation is needed. In the existing methods of ROI coding, after scanning all the pixels in order and discriminating ROI, an ROI mask has been generated. Our method scans 4 pixels of the corners in one code block, and then based on those informations, scans the edges from the corners to get the boundaries of ROI and background. These informations are consisted of a distributed information of ROI and two coordinates of the pixels, which are the points the edges and the boundaries meet. These informations are transmitted to encoder and supported for fast ROI mask generation. There were no great differences between the proposed method and the existing methods in quality, but the proposed method showed superiority in speed.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.06a
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• pp.1191-1194
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• 2022

인터넷의 발전으로 수많은 이미지와 비디오를 손쉽게 이용할 수 있게 되었다. 이미지와 비디오 데이터의 양이 기하급수적으로 증가함에 따라, JPEG, HEVC, VVC 등 이미지와 비디오를 효율적으로 저장하기 위한 부호화 기술들이 등장했다. 최근에는 인공신경망을 활용한 학습 기반 모델이 발전함에 따라, 이를 활용한 이미지 및 비디오 압축 기술에 관한 연구가 빠르게 진행되고 있다. NNIC (Neural Network based Image Coding)는 이러한 학습 가능한 인공신경망 기반 이미지 부호화 기술을 의미한다. 본 논문에서는 NNIC 모델과 인공신경망 기반의 초해상화(Super Resolution) 모델을 합동훈련하여 기존 NNIC 모델보다 더 높은 성능을 보일 수 있는 방법을 제시한다. 먼저 NNIC 인코더(Encoder)에 이미지를 입력하기 전 다운 스케일링(Down Scaling)으로 쌍삼차보간법을 사용하여 이미지의 화소를 줄인 후 부호화(Encoding)한다. NNIC 디코더(Decoder)를 통해 부호화된 이미지를 복호화(Decoding)하고 업 스케일링으로 초해상화를 통해 복호화된 이미지를 원본 이미지로 복원한다. 이때 NNIC 모델과 초해상화 모델을 합동훈련한다. 결과적으로 낮은 비트량에서 더 높은 성능을 볼 수 있는 가능성을 보았다. 또한 합동훈련을 함으로써 전체 성능의 향상을 보아 학습 시간을 늘리고, 압축 잡음을 위한 초해상화 모델을 사용한다면 기존의 NNIC 보다 나은 성능을 보일 수 있는 가능성을 시사한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.474-487
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• 2005

T-DMB (Terrestrial-Digital Multimedia Broadcasting) adopted MPEG-4 BIFS (Binary Format for Scene) Core2D scene description profile and graphics profile as the standard of video associated data service. By using BIFS, we can support to overlay objects, i.e. text, stationary image, circle, polygon, etc., on the main display of receiving end according to the properties designated in broadcasting side and to make clickable buttons and website links on desired objects. Therefore, a variety of interactive data services can be served by BIFS. In this paper, we implement real-time video associated data service system far T-DMB. Our developing system places emphasis on real-time data service by user operation and on inter-working and stability with our previously developed video encoder. Our system consists of BIFS Real-time System, Automatic Stream Control System and Receiving Monitoring System. Basic functions of our system are designed to reflect T-DMB programs and characteristics of program production environment as a top priority. Our developed system was used in BIFS trial service via KBS T-DMB, it is supposed to be used in T-DMB main service after improvement process such as intensifying system stability.