• Title/Summary/Keyword: Iteration Codes

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Effective Iterative Control Method to Reduce the Decoding Delay for Turbo TCM Decoder (터보 TCM 디코더의 복호 지연을 감소시키기 위한 효율적인 반복복호 제어기법)

  • 김순영;김정수;장진수;이문호
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.8
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    • pp.816-822
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    • 2003
  • In this paper, we propose an efficient iteration control method with low complexity for Turbo TCM(Turbo Trellis Coded Modulation) decoding which will be used fur power-limited environment. As the decoding approaches the performance limit of a given turbo code, any further iteration results in very little improvement. Therefore, it is important to devise an efficient criterion to stop the iteration process and prevent unnecessary computations and decoding delay. This paper presents an efficient algorithm for turbo TCM decoding that can greatly reduce the delay and iteration number. The proposed method use adaptive iteration number according to the criterion using the extrinsic information variance parameter in turbo TCM decoding process. The simulation results show that the proposed technique effectively can reduce the decoding delay and computation with very little performance degradation.

Implementation of LDPC Decoder using High-speed Algorithms in Standard of Wireless LAN (무선 랜 규격에서의 고속 알고리즘을 이용한 LDPC 복호기 구현)

  • Kim, Chul-Seung;Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2783-2790
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    • 2010
  • In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

A High Speed Block Turbo Code Decoding Algorithm and Hardware Architecture Design (고속 블록 터보 코드 복호 알고리즘 및 하드웨어 구조 설계)

  • 유경철;신형식;정윤호;김근회;김재석
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.97-103
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    • 2004
  • In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

Performance Of Iterative Decoding Schemes As Various Channel Bit-Densities On The Perpendicular Magnetic Recording Channel (수직자기기록 채널에서 기록 밀도에 따른 반복복호 기법의 성능)

  • Park, Dong-Hyuk;Lee, Jae-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.7C
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    • pp.611-617
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    • 2010
  • In this paper, we investigate the performances of the serial concatenated convolutional codes (SCCC) and low-density parity-check (LDPC) codes on perpendicular magnetic recording (PMR) channels. We discuss the performance of two systems when user bit-densities are 1.7, 2.0, 2.4 and 2.8, respectively. The SCCC system is less complex than LDPC system. The SCCC system consists of recursive systematic convolutional (RSC) codes encoder/decoder, precoder and random interleaver. The decoding algorithm of the SCCC system is the soft message-passing algorithm and the decoding algorithm of the LDPC system is the log domain sum-product algorithm (SPA). When we apply the iterative decoding between channel detector and the error control codes (ECC) decoder, the SCCC system is compatible with the LDPC system even at the high user bit density.

A new approach to determine batch size for the batch method in the Monte Carlo Eigenvalue calculation

  • Lee, Jae Yong;Kim, Do Hyun;Yim, Che Wook;Kim, Jae Chang;Kim, Jong Kyung
    • Nuclear Engineering and Technology
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    • v.51 no.4
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    • pp.954-962
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    • 2019
  • It is well known that the variance of tally is biased in a Monte Carlo calculation based on the power iteration method. Several studies have been conducted to estimate the real variance. Among them, the batch method, which was proposed by Gelbard and Prael, has been utilized actively in many Monte Carlo codes because the method is straightforward, and it is easy to implement the method in the codes. However, there is a problem when utilizing the batch method because the estimated variance varies depending on batch size. Often, the appropriate batch size is not realized before the completion of several Monte Carlo calculations. This study recognizes this shortcoming and addresses it by permitting selection of an appropriate batch size.

Adapt ive Iteration Decoding Preset Method of LDPC Codes by SNR Estimation & Decoder Structure (LDPC 부호의 적응적 반복 복호수 설정 방식 및 복호기 구조)

  • 이정훈;장진수;정영일;이문호
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.773-776
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    • 2001
  • 열악한 전송 환경에서 고품질, 고신뢰성 통신을 지속적으로 하기 위해서 오류 정정 부호는 필수 적이다. 최근에 반복 복호를 통해 샤논의 채널 용량 한계에 근접하는 터보 부호와 LDPC부호가 가장 관심을 불러일으키고 있다. 반복 복호법은 성능 면에서는 우수해 지나 이에 따른 계산량 증가와 지연이 수반된다. 따라서 본 논문에서는 모의 실험을 통한 수신 데이터를 이용, SNR을 추정하여 LDPC 부호의 최대 반복 복호수에 따른 계산량과 지연을 효과적으로 줄일 수 있는 적응적 반복 복호수 설정 방식을 제안한다.

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A Propagation Control Method Using Codes In The Fractal Deformation (코드를 활용한 프랙탈 변형의 전파 제어 방법)

  • Han, Yeong-Deok
    • Journal of Korea Game Society
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    • v.16 no.1
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    • pp.119-128
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    • 2016
  • In this paper, we consider an improved deformation method of IFS(iterated function system) fractal using codes of fractal points. In the existing deformation methods, the intermediate results of position dependent partial deformation propagate randomly due to the randomly selected maps of iteration. Therefore, in many cases, the obtained results become somewhat monotonous feeling shapes. To improve these limitations, we propose a method in which the selection of maps are controlled by codes of fractal points. Applying this method, we can obtain interesting fractal deformation conforming with its fractal features. Also, we propose a simple method, incorporating state variables, that can be applied to deformation of some fractal features other than position coordinates.

Combined Normalized and Offset Min-Sum Algorithm for Low-Density Parity-Check Codes (LDPC 부호의 복호를 위한 정규화와 오프셋이 조합된 최소-합 알고리즘)

  • Lee, Hee-ran;Yun, In-Woo;Kim, Joon Tae
    • Journal of Broadcast Engineering
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    • v.25 no.1
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    • pp.36-47
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    • 2020
  • The improved belief-propagation-based algorithms, such as normalized min-sum algorithm (NMSA) or offset min-sum algorithm (OMSA), are widely used to decode LDPC(Low-Density Parity-Check) codes because they are less computationally complex and work well even at low SNR(Signal-to-Noise Ratio). However, these algorithms work well only when an appropriate normalization factor or offset value is used. A new method that uses a CMD(Check Node Message Distribution) chart and least-square method, which has been recently proposed, has advantages on computational complexity over other approaches to get optimal coefficients. Furthermore, this method can be used to derive coefficients for each iteration. In this paper, we apply this method and propose an algorithm to derive a combination of normalization factor and offset value for a combined normalized and offset min-sum algorithm to further improve the decoding of LDPC codes. Simulations on the next-generation broadcasting standards, ATSC 3.0 LDPC codes, prove that a combined normalized and offset min-sum algorithm which takes the proposed coefficients as correction coefficients shows the best BER performance among other decoding algorithms.

Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder (1.4 Gbps 비이진 LDPC 코드 복호기를 위한 Fully-Parallel 아키텍처)

  • Choi, Injun;Kim, Ji-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.48-58
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    • 2016
  • This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

A New Method for Coronal Force-Free Field Computation That Exactly Implements the Boundary Normal Current Density Condition

  • Yi, Sibaek;Jun, Hongdal;Lee, Junggi;Choe, G.S.
    • The Bulletin of The Korean Astronomical Society
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    • v.44 no.2
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    • pp.71.3-71.3
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    • 2019
  • Previously we developed a method of coronal force-free field construction using vector potentials. In this method, the boundary normal component of the vector potential should be adjusted at every iteration step to implement the boundary normal current density, which is provided by observations. The method was a variational method in the sense that the excessive kinetic energy is removed from the system at every iteration step. The boundary condition imposing the normal current density, however, is not compatible with the variational procedure seeking for the minimum energy state, which is employed by most force-free field solvers currently being used. To resolve this problem, we have developed a totally new method of force-free field construction. Our new method uses a unique magnetic field description using two scalar functions. Our procedure is non-variational and can impose the boundary normal current density exactly. We have tested the new force-free solver for standard Low & Lou fields and Titov-Demoulin flux ropes. Our code excels others in both examples, especially in Titov-Demoulin flux ropes, for which most codes available now yield poor results. Application to a real active region will also be presented.

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