• Title/Summary/Keyword: Inverter Circuit

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A Snubber Circuit for Flying Capacitor Multilevel Inverter and Converter (플라잉 커패시터 멀티레벨 인버터 및 컨버터를 위한 스너버 회로)

  • Lee, Min-Su;Seong, Hyeon-Je;Kim, In-Dong;No, Ui-Cheol;Jo, Cheol-Je
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.50 no.9
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    • pp.459-466
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    • 2001
  • This paper proposes a snubber circuit for flying capacitor multilevel inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber unit. It has such an advantage of Undeland snubber used in the two-level inverter. Compared with conventional RCD/RLD snubber for multileve1 inverter and converter, the proposed snubber keeps such good features as fewer number of components, reduction of voltage stress of main switching devices due to low overvoltage, and improved efficiency of system due to low loss snubber. In this paper, the proposed snubber is applied to three-level flying capacitor inverter and this feature is demonstrated by computer simulation and experimental result.

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Design of Single Flux Quantum D2 Cell and Inverter for ALU (ALU를 위한 단자속 양자 D2 Cell과 Inverter의 설계)

  • 정구락;박종혁;임해용;강준희;한택상
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.02a
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    • pp.140-142
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    • 2003
  • We have designed a SFQ (Single Flux Quantum) D2 Cell and Inverter(NOT) for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we have used Julia, XIC and Lmeter for simulations and layouts. We obtained the circuit margin of larger than $\pm$25%. After layout, we drew chip for fabrication of SFQ D2 Cell and Inverter. We connected D2 Cell and Inverter to jtl, DC/SFQ, SFQ/DC and RS flip-flop for measurement.

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ESD damage mechanism of CMOS DRAM internal circuit and improvement of input protection circuit (정전기에 의한 CMOS DRAM 내부 회오의 파괴 Mechanism과 입력 보호 회로의 개선)

  • 이호재;오춘식
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.12
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    • pp.64-70
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    • 1994
  • In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

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Analysis of Problems when Generating Negative Power for IT devices (IT 기기의 마이너스 전원 생성 시 문제점에 관한 분석)

  • Jun, Ho-Ik;Lee, Hyun-Chang
    • Journal of Software Assessment and Valuation
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    • v.16 no.2
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    • pp.109-115
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    • 2020
  • In this paper, the problem that occurs when negative voltage is generated using an inexpensive buck device in an IT device that is supplied with a single power by an adapter or battery is analyzed. For the cause analysis, the principle of operation of the buck device and the principle of the inverter circuit were examined, and the circuit characteristics of the inverter circuit were analyzed using the buck device. As a result of the analysis, it was confirmed that the inverter circuit using the buck device initially needs a large starting current, and in particular, in the case of a current capacity that is less than the starting current in the circuit that supplies power, it was confirmed that it could fall into a state similar to the latch-up phenomenon. In order to confirm the analysis result, an experimental circuit was constructed and the input current was checked. If the supply current is sufficient, it is confirmed that over-current flows and starts. If the supply current is insufficient, the circuit cannot start and a latch-up phenomenon occurs.

Design and Control of Braking Chopper Circuit for Ventilation Inverter of Traction Control System (고속전철용 추진제어장치의 냉각용 인버터를 위한 제동초퍼 회로 설계 및 제어)

  • Cho, Sung-Joon
    • Proceedings of the KIPE Conference
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    • 2011.07a
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    • pp.314-315
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    • 2011
  • This paper introduces the design and control method of braking chopper circuit which can supply input power to ventilation inverter of traction control system. The DC input voltage from auxiliary block (static inverter) is normally used as an input of ventilation inverter. It converts DC input to AC output voltage to drive cooling fans for traction control system and traction motors. The electrical braking force is very important for high speed train to guarantee safety even though the train is running in the dead section where the pantograph voltage is not supplied. When the high speed train decelerate speed in dead section, the regenerative energy is dissipated by braking resistor. This paper proposed the braking chopper control method to implement rheostatic braking function and the appropriate chopper circuit for supplying voltage source to ventilation inverter during rheostatic braking mode. The proposed chopper circuit makes it possible for traction control system to regenerate power continuously regardless of the existence of pantograph voltage. The feasibility of proposed braking chopper control and circuit were proven by inertia load test and actual train field test.

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A Study on Characteristic Analysis of Current Fed High Frequency Resonant Inverter for Wax-Sealing (Wax-Sealing용 전류형 고주파 공진 인버터의 특성해석에 관한 연구)

  • Kim, Dong-Hui;Won, Jae-Seon
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.50 no.11
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    • pp.568-574
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    • 2001
  • This paper describes a current fed high frequency resonant inverter can be used as the power supply for wax-sealing. This circuit configuration is composed of conventional two unit inverter of single ended current find type in parallel. The proposed inverter can realize ZVS operation by using resonant capacitor to ZVS capacitor and has merits not only reduction of switch current distribution but also extension of load range in comparison with the conventional single-ended current fed high frequency resonant inverter. This analysis of proposed circuit uses normalized parameter and characteristic estimation which is needed in each step before design is generally described according to normalized frequency($\mu$), normalized resistance(λ) and parameters. On the basis of characteristic values, a method of the circuit design is presented. Also, the theoretical analysis is proved through experiment and this proposed circuit shows that it can be practically used as the power supply system for wax-sealing and DC-DC converter.

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Modeling of Multilevel PWM Inverter/Rectifier (멀티레벨 PWM 인버터/정류기의 모델링)

  • Choi, Nam-Sup;Cho, Gyu-Hyeong
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.1119-1122
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    • 1992
  • This paper deals with a novel method of modeling and analyzing multilevel pulse width modulation(PWM) inverter/rectifier, which leads to extraction of equivalent circuit in fundamental frequency domain. By the technique, we can draw out the corresponding linear time invariant circuit even thuogh the actual circuit is switched. A static VAR compensator using five-level inverter is modeled and simulated for the verification of the modeling.

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Design and Effects of Power Factor Correction Circuit for Inverter Air-Conditioner (인버터 에어컨용 능동역률보상회로 설계 및 효과)

  • 박병욱;권경안
    • Proceedings of the KIPE Conference
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    • 1998.07a
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    • pp.27-30
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    • 1998
  • In this paper, the inverter air-conditioner with Power Factor Correction(PFC) circuit is Presented for obtaining the good system efficiency and cost merit compared with the conventional inverter air-conditioner. The detailed design procedures for getting the optimal passive components are implemented. Through the simulation and experimental results, it is shown that the system efficiency can be improved. Using the designed components, the prototype system is builted and tested to verify the additional good performances of the proposed circuit.

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Charge-Pump High Voltage Inverter for Plasma Backlight using Current Injection Method (CIM(Current Injection Method)을 이용한 Charge-Pump 방식의 Plasma Backlight용 고압Inverter)

  • Jang, Jun-Ho;Kang, Shin-Ho;Lee, Kyung-In;Lee, Jun-Young
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.5
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    • pp.386-393
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    • 2007
  • Charge-pump high voltage inverter for Plasma backlight using CIM(Current Injection Method) is proposed in this paper. Adoption of ERC(Energy Recovery Circuit) is a new attempt in high voltage inverter so that it is not only energy recovery but also improvement of discharge stability and system unstability which is interrupted by noise. Using a charge-pump technique enables low voltage switches to be usable, the cost can be reduced. CIM is adopted to achieve high speed energy recovery in proposed circuit. Operations of the proposed circuit are analyzed for each mode. The proposed circuit is verified to be applicable on a 32 inch plasma backlight panel by experimental results.

ESP by using Half-bridge ZCS resonant inverter and Cockroft-Walton circuit (Half-Bridge ZCS resonant inverter 및 Cockroft-Walton회로를 사용한 공기 청정기에 관한 연구)

  • Park, Jong-Woong;Jeong, Jong-Jin;Chung, Hyun-Ju;Joung, Jong-Han;Kim, Hee-Je
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.1951-1953
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    • 2004
  • In this study, we propose a small high voltage power supply which use a half-bridge ZCS resonant and Cockroft-Walton on circuit, for ESP (Electrostatic Precipitator). This power supply transfers energy from ZCS resonant inverter to step-up transformer and the transformer secondary is applied to the Cockroft-Walton circuit for generating high voltage as discharging source of electrodes. It is highly efficient because its amount of switching losses are reduced by virtue of the current resonant half-bridge inverter, and also due to the small size, low parasitic capacitance in the transformer stage owing to the low number of winding turns of the step up transformer secondary combined with the Cockroft-Walton circuit. From these results, the best operational condition is obtained at the switching frequency of 9 kHz and the duty ratio of 50 % in this ESP.

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