• ETRI Journal
• /
• v.27 no.5
• /
• pp.491-496
• /
• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• Journal of the Korean earth science society
• /
• v.34 no.1
• /
• pp.69-80
• /
• 2013

Terrain data is one of important basic data in various areas of Earth science. Recently, finer DEM data is available, which necessary to develop a method that deals with such huge data efficiently. This study was conducted on the lossless compression of DEM data and efficient partial reconstruction of terrain information from compressed data. In this study, we compressed the wavelet coefficients of DEM, obtained from integer wavelet transform (IWT) by entropy encoding. CDF (Cohen-Daubechies-Feauveau) 3.5 wavelet showed the best compression ratio of about 45.4% and the optimum decomposition level was 3. Results also showed that a small region of terrain could be restored from the inverse wavelet transform with a part of the wavelet coefficients that are related to such region instead of whole reconstruction. We discussed the potential applications of the terrain data compression for precise gravity terrain correction.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.23 no.6
• /
• pp.75-80
• /
• 2023

We show the design of fast invertible block transforms that can replace the DCT in future wireless and portable computing application. This is called binDCT. In binDCT, both the forward and the inverse transforms can be implemented using only binary shift and addition operation. And the binDCT inherits all desirable DCT characteristics such as high coding gain, no DC leakage, symmetric basis functions, and recursive construction. The binDCT also inherits all lifting properties such as fast implementations, invertible integer-to-integer mapping, in-place computation. Thus, this method has advantage of fast implementation for complex DCT calculations. In this paper, we present computation costs and performance analysis between DCT and binDCT using Shapiro's EZW.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.10
• /
• pp.36-42
• /
• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.