• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.29-35
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• 2007

Recently, as the demand of mobile multimedia devices increases and T-DMB is started in Korea, the need of research for integration of mobile devices such as cellular phone, navigation, and portable multimedia player becomes higher. In order to integrate mobile devices, it is necessary to support microprocessor with fast speed and various devices with multimedia service. In this paper, we construct Windows CE 5.0 platform whose BSP supports the embedded system board with ARM11 core and various devices and applications. We also implement the DMB device driver which supports busy waiting and interrupt driven I/O techniques, compare their performance, and then suggest the method to efficiently use the resources of embedded system.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.626-634
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• 2004

In a client-server model, network server systems suffer from both heavy communication and computational loads. While communication channels become increasingly speedy, the existing protocol stack architectures still include mainly three performance bottlenecks of protocol stack processing, system call, and network interrupt overheads. To address these obstacles, in this paper we present a host-independent network system where a network interface card (NIC) is utilized in an efficient manner. First, by offloading network-related portion to the NIC, the host can fully utilize its processing power for other useful purposes. Second, it eliminates the system call overhead, such as context-switching and memory copy operations, since the host communicates with the NIC through its user-level libraries. Third, it a] so reduces the network interrupt operation count as the host handles the interrupt in a segment instead of a packet. The experimental results show that the proposed network system reduces the host CPU overhead for communication system by 68-71%. It also shows that the proposed system improves the communication speed by 11-83% under heavy computational and communication load conditions.

• Journal of Astronomy and Space Sciences
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• v.29 no.3
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• pp.315-320
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• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.